[llvm] [CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation (PR #139206)

[Vikash Gupta via llvm-commits]

https://github.com/vg0204 updated https://github.com/llvm/llvm-project/pull/139206

>From 5b309afaf0691c1c9ec0ec1c3e196a5314c0e385 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Fri, 9 May 2025 06:04:19 +0000
Subject: [PATCH] [CodeGen] For ad hoc aliasing, now each lead node register
 will have register unit defined that uniquely identifies them, alongwith a an
 addtional register unit per edge in ad hoc alias graph that shows the
 register overlap between the connected aliasing leaf register nodes

It solves the issue of using the aliasing register as the immediate
subregister of a register, thus need to have disjoint lanemask, which
is now possible by virtue of uniquely defined register units. At the
same time, aliasing is accounted by the shared register unit, having
lanemask as 0x0 just as previously, not a problem now.
---
 .../TableGen/Common/CodeGenRegisters.cpp      | 36 ++++++++++++++-----
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 639f94f79ecd7..fc2e14787cafc 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -424,20 +424,33 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
   // These units correspond to the maximal cliques in the register overlap
   // graph which is optimal.
   //
-  // When there is ad hoc aliasing, we simply create one unit per edge in the
-  // undirected ad hoc aliasing graph. Technically, we could do better by
-  // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
-  // are extremely rare anyway (I've never seen one), so we don't bother with
-  // the added complexity.
+  // When there is ad hoc aliasing, while we create one unit per edge in the
+  // undirected ad hoc aliasing graph to represent aliasing, one unit per each
+  // node leaf register is needed extra to identify them uniquely, in case these
+  // aliasing register are used as subregister(with disjoint lanemasks) to have
+  // an accurate lanemask generation for these leaf register.
+  // For example, In VE, SX0 is made out of disjoint subregister SW0 & SF0
+  // respectively, where SF0 is an alias for SW0. So while 2 register units will
+  // uniquely define these 2 subregister, the shared register unit will account
+  // for aliasing.
+  //
+  // Technically, we could do better by identifying maximal cliques in the ad
+  // hoc graph, but cliques larger than 2 are extremely rare anyway (I've never
+  // seen one), so we don't bother with the added complexity.
   for (CodeGenRegister *AR : ExplicitAliases) {
     // Only visit each edge once.
     if (AR->SubRegsComplete)
       continue;
     // Create a RegUnit representing this alias edge, and add it to both
     // registers.
-    unsigned Unit = RegBank.newRegUnit(this, AR);
-    RegUnits.set(Unit);
-    AR->RegUnits.set(Unit);
+    unsigned SharedUnit = RegBank.newRegUnit(this, AR);
+    RegUnits.set(SharedUnit);
+    AR->RegUnits.set(SharedUnit);
+
+    // Create a RegUnit that now corresponds uniquely to each of the both
+    // alias leaf register nodes.
+    RegUnits.set(RegBank.newRegUnit(this));
+    AR->RegUnits.set(RegBank.newRegUnit(AR));
   }
 
   // Finally, create units for leaf registers without ad hoc aliases. Note that
@@ -2675,6 +2688,13 @@ void CodeGenRegBank::printRegUnitNames(ArrayRef<unsigned> Units) const {
       dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
     else
       dbgs() << " #" << Unit;
+
+    if (RegUnits[Unit].Roots[1]) {
+      if (Unit < NumNativeRegUnits)
+        dbgs() << '~' << RegUnits[Unit].Roots[1]->getName();
+      else
+        dbgs() << "~#" << Unit;
+    }
   }
   dbgs() << '\n';
 }