[llvm] [RISCV][Peephole] Checking regclass compatibility in VMV (PR #138844)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu May 8 22:49:39 PDT 2025
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/138844
>From fbf99ce1f66fd4829e7ed210d1fdfe16d3ff7236 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 7 May 2025 03:19:24 -0700
Subject: [PATCH 1/5] precommit
---
.../rvv-peephole-vmv-with-different-class.mir | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
new file mode 100644
index 0000000000000..8b6b33e2ff740
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
@@ -0,0 +1,144 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
+# RUN: | FileCheck %s
+
+--- |
+ source_filename = "reduced.ll"
+ target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+ target triple = "riscv64-unknown-linux-gnu"
+
+ define i32 @main() #0 {
+ entry:
+ %0 = tail call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer, i64 0)
+ %1 = tail call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
+ %2 = tail call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x i32> %1, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
+ %3 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) zeroinitializer, <vscale x 1 x i64> %2, i32 0)
+ call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr null, i64 0, i64 6)
+ ret i32 0
+ }
+
+ declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
+
+ declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
+
+ declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
+
+ declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), <vscale x 1 x i64>, i32 immarg) #2
+
+ declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #3
+
+ attributes #0 = { "target-features"="+v" }
+ attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" }
+ attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-features"="+v" }
+ attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) "target-features"="+v" }
+
+...
+---
+name: main
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: false
+isSSA: true
+noVRegs: false
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+ - { id: 0, class: vr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 2, class: vr, preferred-register: '', flags: [ ] }
+ - { id: 3, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 4, class: vmv0, preferred-register: '', flags: [ ] }
+ - { id: 5, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 6, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 7, class: vmv0, preferred-register: '', flags: [ ] }
+ - { id: 8, class: vr, preferred-register: '', flags: [ ] }
+ - { id: 9, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 10, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 11, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 12, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 13, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 14, class: gpr, preferred-register: '', flags: [ ] }
+liveins: []
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 4294967295
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ isCalleeSavedInfoValid: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack: []
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo:
+ varArgsFrameIndex: 0
+ varArgsSaveSize: 0
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: main
+ ; CHECK: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK [[PseudoVMV_V_I_M1_]], killed [[PseudoVXOR_VV_MF2_MASK]], [[PseudoVMV_V_I_MF2_]], [[COPY1]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_I_M1_1:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_0
+ ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_1
+ ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_2
+ ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG2]], killed %6, %subreg.sub_vrm1_0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: PseudoVSSEG3E64_V_M1 killed [[INSERT_SUBREG3]], [[COPY2]], 0, 6 /* e64 */ :: (store unknown-size into `ptr null`, align 8)
+ ; CHECK-NEXT: $x10 = COPY [[COPY2]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
+ %2:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ %4:vmv0 = COPY %2
+ %3:vrnov0 = PseudoVXOR_VV_MF2_MASK %1, %0, %0, %4, 0, 5 /* e32 */, 0 /* tu, mu */
+ %5:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
+ %7:vmv0 = COPY %2
+ early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK %5, killed %3, %0, %7, 0, 5 /* e32 */, 0 /* tu, mu */
+ %8:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
+ %10:vrn3m1 = IMPLICIT_DEF
+ %9:vrn3m1 = INSERT_SUBREG %10, %8, %subreg.sub_vrm1_0
+ %11:vrn3m1 = INSERT_SUBREG %9, %8, %subreg.sub_vrm1_1
+ %12:vrn3m1 = INSERT_SUBREG %11, %8, %subreg.sub_vrm1_2
+ %13:vrn3m1 = INSERT_SUBREG %12, killed %6, %subreg.sub_vrm1_0
+ %14:gpr = COPY $x0
+ PseudoVSSEG3E64_V_M1 killed %13, %14, 0, 6 /* e64 */ :: (store unknown-size into `ptr null`, align 8)
+ $x10 = COPY %14
+ PseudoRET implicit $x10
+...
>From b4c5590e65f598902ef305eddff7af2b796eb42f Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 7 May 2025 03:35:05 -0700
Subject: [PATCH 2/5] [RISCV][Peephole] Checking regclass compatibility in VMV
---
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 10 ++++++++++
.../rvv/rvv-peephole-vmv-with-different-class.mir | 5 +++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 41f8e1a5ef14d..a3c2d9cfe5bcf 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -565,6 +565,11 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
if (MI.getOperand(1).getReg() != RISCV::NoRegister)
return false;
+ const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
+ const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
+ if (!RC1->hasSubClassEq(RC2))
+ return false;
+
// If the input was a pseudo with a policy operand, we can give it a tail
// agnostic policy if MI's undef tail subsumes the input's.
MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
@@ -608,6 +613,11 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
if (!MRI->hasOneUse(MI.getOperand(2).getReg()))
return false;
+ const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
+ const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
+ if (!RC1->hasSubClassEq(RC2))
+ return false;
+
MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
if (!Src || Src->hasUnmodeledSideEffects() ||
Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
index 8b6b33e2ff740..6f83842112efe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
-# RUN: | FileCheck %s
+# RUN: -verify-machineinstrs | FileCheck %s
--- |
source_filename = "reduced.ll"
@@ -107,9 +107,10 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: main
; CHECK: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 $noreg, [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
- ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK [[PseudoVMV_V_I_M1_]], killed [[PseudoVXOR_VV_MF2_MASK]], [[PseudoVMV_V_I_MF2_]], [[COPY1]], 0, 5 /* e32 */, 0 /* tu, mu */
>From 2bd6fc4c65af4428bd8205eaeb96c0aa55b42e7a Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 7 May 2025 22:01:55 -0700
Subject: [PATCH 3/5] !fixup reduce the testcase and move into
vmv.v.v-peephole.mir
---
.../rvv-peephole-vmv-with-different-class.mir | 145 ------------------
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 36 +++++
2 files changed, 36 insertions(+), 145 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
deleted file mode 100644
index 6f83842112efe..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir
+++ /dev/null
@@ -1,145 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
-# RUN: -verify-machineinstrs | FileCheck %s
-
---- |
- source_filename = "reduced.ll"
- target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
- target triple = "riscv64-unknown-linux-gnu"
-
- define i32 @main() #0 {
- entry:
- %0 = tail call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer, i64 0)
- %1 = tail call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
- %2 = tail call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x i32> %1, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
- %3 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) zeroinitializer, <vscale x 1 x i64> %2, i32 0)
- call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr null, i64 0, i64 6)
- ret i32 0
- }
-
- declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
-
- declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
-
- declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
-
- declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), <vscale x 1 x i64>, i32 immarg) #2
-
- declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #3
-
- attributes #0 = { "target-features"="+v" }
- attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" }
- attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-features"="+v" }
- attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) "target-features"="+v" }
-
-...
----
-name: main
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-noPhis: false
-isSSA: true
-noVRegs: false
-hasFakeUses: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHScopes: false
-hasEHFunclets: false
-isOutlined: false
-debugInstrRef: false
-failsVerification: false
-tracksDebugUserValues: false
-registers:
- - { id: 0, class: vr, preferred-register: '', flags: [ ] }
- - { id: 1, class: vrnov0, preferred-register: '', flags: [ ] }
- - { id: 2, class: vr, preferred-register: '', flags: [ ] }
- - { id: 3, class: vrnov0, preferred-register: '', flags: [ ] }
- - { id: 4, class: vmv0, preferred-register: '', flags: [ ] }
- - { id: 5, class: vrnov0, preferred-register: '', flags: [ ] }
- - { id: 6, class: vrnov0, preferred-register: '', flags: [ ] }
- - { id: 7, class: vmv0, preferred-register: '', flags: [ ] }
- - { id: 8, class: vr, preferred-register: '', flags: [ ] }
- - { id: 9, class: vrn3m1, preferred-register: '', flags: [ ] }
- - { id: 10, class: vrn3m1, preferred-register: '', flags: [ ] }
- - { id: 11, class: vrn3m1, preferred-register: '', flags: [ ] }
- - { id: 12, class: vrn3m1, preferred-register: '', flags: [ ] }
- - { id: 13, class: vrn3m1, preferred-register: '', flags: [ ] }
- - { id: 14, class: gpr, preferred-register: '', flags: [ ] }
-liveins: []
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- isCalleeSavedInfoValid: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack: []
-stack: []
-entry_values: []
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- varArgsFrameIndex: 0
- varArgsSaveSize: 0
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: main
- ; CHECK: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 $noreg, [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
- ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
- ; CHECK-NEXT: early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK [[PseudoVMV_V_I_M1_]], killed [[PseudoVXOR_VV_MF2_MASK]], [[PseudoVMV_V_I_MF2_]], [[COPY1]], 0, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[PseudoVMV_V_I_M1_1:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_0
- ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_1
- ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_2
- ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG2]], killed %6, %subreg.sub_vrm1_0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: PseudoVSSEG3E64_V_M1 killed [[INSERT_SUBREG3]], [[COPY2]], 0, 6 /* e64 */ :: (store unknown-size into `ptr null`, align 8)
- ; CHECK-NEXT: $x10 = COPY [[COPY2]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
- %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
- %2:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
- %4:vmv0 = COPY %2
- %3:vrnov0 = PseudoVXOR_VV_MF2_MASK %1, %0, %0, %4, 0, 5 /* e32 */, 0 /* tu, mu */
- %5:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
- %7:vmv0 = COPY %2
- early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK %5, killed %3, %0, %7, 0, 5 /* e32 */, 0 /* tu, mu */
- %8:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
- %10:vrn3m1 = IMPLICIT_DEF
- %9:vrn3m1 = INSERT_SUBREG %10, %8, %subreg.sub_vrm1_0
- %11:vrn3m1 = INSERT_SUBREG %9, %8, %subreg.sub_vrm1_1
- %12:vrn3m1 = INSERT_SUBREG %11, %8, %subreg.sub_vrm1_2
- %13:vrn3m1 = INSERT_SUBREG %12, killed %6, %subreg.sub_vrm1_0
- %14:gpr = COPY $x0
- PseudoVSSEG3E64_V_M1 killed %13, %14, 0, 6 /* e64 */ :: (store unknown-size into `ptr null`, align 8)
- $x10 = COPY %14
- PseudoRET implicit $x10
-...
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index a2acb004642d6..75b851ca2d202 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -105,3 +105,39 @@ body: |
%3:vr = COPY %0
...
---
+name: diff_regclass
+body: |
+ bb.0.entry:
+ liveins: $v8
+ ; CHECK-LABEL: name: diff_regclass
+ ; CHECK: liveins: $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 $noreg, [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
+ ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+ %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
+ %4:vmv0 = COPY $v8
+ %3:vrnov0 = PseudoVXOR_VV_MF2_MASK %1, %0, %0, %4, 0, 5 /* e32 */, 0 /* tu, mu */
+...
+---
+name: diff_regclass_passthru
+body: |
+ bb.0.entry:
+ liveins: $v8
+ ; CHECK-LABEL: name: diff_regclass_passthru
+ ; CHECK: liveins: $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
+ ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 [[COPY]], killed [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vmv0 = COPY $v8
+ ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[COPY1]], [[COPY1]], killed [[COPY2]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
+ %0:vr = COPY $v8
+ %2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ %3:vrnov0 = PseudoVMV_V_V_MF2 %0, killed %2, 0, 5 /* e32 */, 0 /* tu, mu */
+ %5:gpr = COPY $x0
+ %7:vmv0 = COPY $v8
+ %6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, %5, %5, killed %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
>From 921ceddb3f2443c83422d09f325319b2494bab33 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 8 May 2025 19:13:01 -0700
Subject: [PATCH 4/5] !fixup Use constrainRegClass
---
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 14 ++++----------
llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 10 ++++------
2 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index a3c2d9cfe5bcf..721b0bf425e95 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -565,11 +565,6 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
if (MI.getOperand(1).getReg() != RISCV::NoRegister)
return false;
- const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
- const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
- if (!RC1->hasSubClassEq(RC2))
- return false;
-
// If the input was a pseudo with a policy operand, we can give it a tail
// agnostic policy if MI's undef tail subsumes the input's.
MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
@@ -588,6 +583,8 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC);
}
+ MRI->constrainRegClass(MI.getOperand(2).getReg(),
+ MRI->getRegClass(MI.getOperand(0).getReg()));
MRI->replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
MRI->clearKillFlags(MI.getOperand(2).getReg());
MI.eraseFromParent();
@@ -613,11 +610,6 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
if (!MRI->hasOneUse(MI.getOperand(2).getReg()))
return false;
- const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
- const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
- if (!RC1->hasSubClassEq(RC2))
- return false;
-
MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
if (!Src || Src->hasUnmodeledSideEffects() ||
Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||
@@ -663,6 +655,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
Policy |= RISCVVType::TAIL_AGNOSTIC;
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);
+ MRI->constrainRegClass(Src->getOperand(0).getReg(),
+ MRI->getRegClass(MI.getOperand(0).getReg()));
MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
MI.eraseFromParent();
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index 75b851ca2d202..dd15cfe740ea0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -112,10 +112,9 @@ body: |
; CHECK-LABEL: name: diff_regclass
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 $noreg, [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
- ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
%0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
%1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
%4:vmv0 = COPY $v8
@@ -130,11 +129,10 @@ body: |
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
- ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 [[COPY]], killed [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 [[COPY]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vmv0 = COPY $v8
- ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[COPY1]], [[COPY1]], killed [[COPY2]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
+ ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY1]], [[COPY1]], killed [[COPY2]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
%0:vr = COPY $v8
%2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
%3:vrnov0 = PseudoVMV_V_V_MF2 %0, killed %2, 0, 5 /* e32 */, 0 /* tu, mu */
>From 04b2d43b8e070310d0fdf0580de96683782c6957 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 8 May 2025 19:32:17 -0700
Subject: [PATCH 5/5] !fixup reduce testcase
---
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index dd15cfe740ea0..719e02118b538 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -112,13 +112,13 @@ body: |
; CHECK-LABEL: name: diff_regclass
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 1 /* ta, mu */
; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
- ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
%0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
%1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
- %4:vmv0 = COPY $v8
- %3:vrnov0 = PseudoVXOR_VV_MF2_MASK %1, %0, %0, %4, 0, 5 /* e32 */, 0 /* tu, mu */
+ %2:vmv0 = COPY $v8
+ %3:vrnov0 = PseudoVADD_VV_M1_MASK %1, $noreg, $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
...
---
name: diff_regclass_passthru
@@ -130,12 +130,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 [[COPY]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vmv0 = COPY $v8
- ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY1]], [[COPY1]], killed [[COPY2]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY $v8
+ ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY1]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
%0:vr = COPY $v8
%2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
- %3:vrnov0 = PseudoVMV_V_V_MF2 %0, killed %2, 0, 5 /* e32 */, 0 /* tu, mu */
- %5:gpr = COPY $x0
+ %3:vrnov0 = PseudoVMV_V_V_MF2 %0, %2, 0, 5 /* e32 */, 0 /* tu, mu */
%7:vmv0 = COPY $v8
- %6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, %5, %5, killed %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
+ %6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, $noreg, $noreg, %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
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