[llvm] [NFC][RISCV] Pre-commit tests for RVI constant multiplication expansion (PR #139200)
Iris Shi via llvm-commits
llvm-commits at lists.llvm.org
Thu May 8 20:06:12 PDT 2025
https://github.com/el-ev created https://github.com/llvm/llvm-project/pull/139200
#137195
>From 15da2241bf57728e82e9e29b32007c9d1797a234 Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0 at owo.li>
Date: Fri, 9 May 2025 11:05:12 +0800
Subject: [PATCH] [NFC][RISCV] Pre-commit tests for RVI constant multiplication
expansion
---
llvm/test/CodeGen/RISCV/mul-expand.ll | 490 ++++++++++++++++++++++++++
1 file changed, 490 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/mul-expand.ll
diff --git a/llvm/test/CodeGen/RISCV/mul-expand.ll b/llvm/test/CodeGen/RISCV/mul-expand.ll
new file mode 100644
index 0000000000000..5bb74bc184d8b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/mul-expand.ll
@@ -0,0 +1,490 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+
+define i32 @muli32_0x555(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x555:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 1365
+; RV32I-NEXT: tail __mulsi3
+;
+; RV64I-LABEL: muli32_0x555:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 1365
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 1365
+ ret i32 %a1
+}
+
+define i64 @muli64_0x555(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x555:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li a2, 1365
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0x555:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 1365
+; RV64I-NEXT: tail __muldi3
+ %a1 = mul i64 %a, 1365
+ ret i64 %a1
+}
+
+define i32 @muli32_0x33333333(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x33333333:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 209715
+; RV32I-NEXT: addi a1, a1, 819
+; RV32I-NEXT: tail __mulsi3
+;
+; RV64I-LABEL: muli32_0x33333333:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 209715
+; RV64I-NEXT: addiw a1, a1, 819
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 858993459
+ ret i32 %a1
+}
+
+define i64 @muli64_0x33333333(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x33333333:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a2, 209715
+; RV32I-NEXT: addi a2, a2, 819
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0x33333333:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 209715
+; RV64I-NEXT: addiw a1, a1, 819
+; RV64I-NEXT: tail __muldi3
+ %a1 = mul i64 %a, 858993459
+ ret i64 %a1
+}
+
+define i32 @muli32_0xaaaaaaaa(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xaaaaaaaa:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 699051
+; RV32I-NEXT: addi a1, a1, -1366
+; RV32I-NEXT: tail __mulsi3
+;
+; RV64I-LABEL: muli32_0xaaaaaaaa:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 699051
+; RV64I-NEXT: addiw a1, a1, -1366
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, -1431655766
+ ret i32 %a1
+}
+
+define i64 @muli64_0xaaaaaaaa(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xaaaaaaaa:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a2, 699051
+; RV32I-NEXT: addi a2, a2, -1366
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0xaaaaaaaa:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 349525
+; RV64I-NEXT: addiw a1, a1, 1365
+; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: tail __muldi3
+ %a1 = mul i64 %a, 2863311530
+ ret i64 %a1
+}
+
+define i32 @muli32_0x0fffffff(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x0fffffff:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 28
+; RV32I-NEXT: sub a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli32_0x0fffffff:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 28
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 268435455
+ ret i32 %a1
+}
+
+define i64 @muli64_0x0fffffff(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x0fffffff:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a2, a0, 28
+; RV32I-NEXT: srli a3, a0, 4
+; RV32I-NEXT: slli a4, a1, 28
+; RV32I-NEXT: sltu a5, a2, a0
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: sub a1, a3, a1
+; RV32I-NEXT: sub a1, a1, a5
+; RV32I-NEXT: sub a0, a2, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0x0fffffff:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 28
+; RV64I-NEXT: sub a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i64 %a, 268435455
+ ret i64 %a1
+}
+
+define i32 @muli32_0xf0f0f0f0(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xf0f0f0f0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 986895
+; RV32I-NEXT: addi a1, a1, 240
+; RV32I-NEXT: tail __mulsi3
+;
+; RV64I-LABEL: muli32_0xf0f0f0f0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 986895
+; RV64I-NEXT: addiw a1, a1, 240
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, -252645136
+ ret i32 %a1
+}
+
+define i64 @muli64_0xf0f0f0f0(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xf0f0f0f0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a2, 986895
+; RV32I-NEXT: addi a2, a2, 240
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0xf0f0f0f0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: tail __muldi3
+ %a1 = mul i64 %a, 4042322160
+ ret i64 %a1
+}
+
+define i32 @muli32_0xf7f7f7f7(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xf7f7f7f7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1015679
+; RV32I-NEXT: addi a1, a1, 2039
+; RV32I-NEXT: tail __mulsi3
+;
+; RV64I-LABEL: muli32_0xf7f7f7f7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 1015679
+; RV64I-NEXT: addiw a1, a1, 2039
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, -134744073
+ ret i32 %a1
+}
+
+define i64 @muli64_0xf7f7f7f7(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xf7f7f7f7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a2, 1015679
+; RV32I-NEXT: addi a2, a2, 2039
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0xf7f7f7f7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 248
+; RV64I-NEXT: addiw a1, a1, -129
+; RV64I-NEXT: slli a1, a1, 12
+; RV64I-NEXT: addi a1, a1, 2039
+; RV64I-NEXT: tail __muldi3
+ %a1 = mul i64 %a, 4160223223
+ ret i64 %a1
+}
+
+define i32 @muli32_0x1000(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x1000:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a0, a0, 12
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli32_0x1000:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slliw a0, a0, 12
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 4096
+ ret i32 %a1
+}
+
+define i64 @muli64_0x1000(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x1000:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a2, a0, 20
+; RV32I-NEXT: slli a1, a1, 12
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: slli a0, a0, 12
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0x1000:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 12
+; RV64I-NEXT: ret
+ %a1 = mul i64 %a, 4096
+ ret i64 %a1
+}
+
+define i32 @muli32_0x101(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x101:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: add a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli32_0x101:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: addw a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 257
+ ret i32 %a1
+}
+
+define i64 @muli64_0x101(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x101:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a2, a0, 8
+; RV32I-NEXT: srli a3, a0, 24
+; RV32I-NEXT: slli a4, a1, 8
+; RV32I-NEXT: add a0, a2, a0
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: sltu a2, a0, a2
+; RV32I-NEXT: add a1, a3, a1
+; RV32I-NEXT: add a1, a1, a2
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0x101:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: add a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i64 %a, 257
+ ret i64 %a1
+}
+
+define i32 @muli32_0xfff(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xfff:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 12
+; RV32I-NEXT: sub a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli32_0xfff:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 12
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 4095
+ ret i32 %a1
+}
+
+define i64 @muli64_0xfff(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xfff:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a2, a0, 12
+; RV32I-NEXT: srli a3, a0, 20
+; RV32I-NEXT: slli a4, a1, 12
+; RV32I-NEXT: sltu a5, a2, a0
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: sub a1, a3, a1
+; RV32I-NEXT: sub a1, a1, a5
+; RV32I-NEXT: sub a0, a2, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0xfff:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 12
+; RV64I-NEXT: sub a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i64 %a, 4095
+ ret i64 %a1
+}
+
+define i32 @muli32_0x7fffffff(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x7fffffff:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 31
+; RV32I-NEXT: sub a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli32_0x7fffffff:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 31
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 2147483647
+ ret i32 %a1
+}
+
+define i64 @muli64_0x7fffffff(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x7fffffff:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a2, a0, 31
+; RV32I-NEXT: srli a3, a0, 1
+; RV32I-NEXT: slli a4, a1, 31
+; RV32I-NEXT: sltu a5, a2, a0
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: sub a1, a3, a1
+; RV32I-NEXT: sub a1, a1, a5
+; RV32I-NEXT: sub a0, a2, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0x7fffffff:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 31
+; RV64I-NEXT: sub a0, a1, a0
+; RV64I-NEXT: ret
+ %a1 = mul i64 %a, 2147483647
+ ret i64 %a1
+}
+
+define i32 @muli32_0xdeadbeef(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xdeadbeef:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 912092
+; RV32I-NEXT: addi a1, a1, -273
+; RV32I-NEXT: tail __mulsi3
+;
+; RV64I-LABEL: muli32_0xdeadbeef:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 912092
+; RV64I-NEXT: addiw a1, a1, -273
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, -559038737
+ ret i32 %a1
+}
+
+define i64 @muli64_0xdeadbeef(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xdeadbeef:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a2, 912092
+; RV32I-NEXT: addi a2, a2, -273
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0xdeadbeef:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 228023
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: addi a1, a1, -273
+; RV64I-NEXT: tail __muldi3
+ %a1 = mul i64 %a, 3735928559
+ ret i64 %a1
+}
+
+define i32 @muli32_0x12345678(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x12345678:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 74565
+; RV32I-NEXT: addi a1, a1, 1656
+; RV32I-NEXT: tail __mulsi3
+;
+; RV64I-LABEL: muli32_0x12345678:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 74565
+; RV64I-NEXT: addiw a1, a1, 1656
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %a1 = mul i32 %a, 305419896
+ ret i32 %a1
+}
+
+define i64 @muli64_0x12345678(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x12345678:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a2, 74565
+; RV32I-NEXT: addi a2, a2, 1656
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: muli64_0x12345678:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 74565
+; RV64I-NEXT: addiw a1, a1, 1656
+; RV64I-NEXT: tail __muldi3
+ %a1 = mul i64 %a, 305419896
+ ret i64 %a1
+}
More information about the llvm-commits
mailing list