[llvm] [NFC][RISCV] Add more test cases for multiplication (PR #139195)
Iris Shi via llvm-commits
llvm-commits at lists.llvm.org
Thu May 8 19:02:53 PDT 2025
https://github.com/el-ev created https://github.com/llvm/llvm-project/pull/139195
None
>From 5c3a1eb6b229ad790c0c830d85a4652ec5ac06fa Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0 at owo.li>
Date: Wed, 30 Apr 2025 19:11:41 +0800
Subject: [PATCH] add tests
---
llvm/test/CodeGen/RISCV/mul.ll | 136 +++++++++++++++++++++++++++++++--
1 file changed, 131 insertions(+), 5 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index 548c7e1c6ea8c..9447dcaf72373 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -494,6 +494,37 @@ define i32 @muli32_p14(i32 %a) nounwind {
ret i32 %1
}
+define i32 @muli32_p18(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p18:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 18
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p18:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 18
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p18:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 18
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p18:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 18
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 18
+ ret i32 %1
+}
+
define i32 @muli32_p28(i32 %a) nounwind {
; RV32I-LABEL: muli32_p28:
; RV32I: # %bb.0:
@@ -554,6 +585,68 @@ define i32 @muli32_p30(i32 %a) nounwind {
ret i32 %1
}
+define i32 @muli32_p34(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p34:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 34
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p34:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 34
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p34:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 34
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p34:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 34
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 34
+ ret i32 %1
+}
+
+define i32 @muli32_p36(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p36:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 36
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p36:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 36
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p36:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 36
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p36:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 36
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 36
+ ret i32 %1
+}
+
define i32 @muli32_p56(i32 %a) nounwind {
; RV32I-LABEL: muli32_p56:
; RV32I: # %bb.0:
@@ -778,7 +871,40 @@ define i64 @muli64_p63(i64 %a) nounwind {
ret i64 %1
}
-
+define i64 @muli64_p72(i64 %a) nounwind {
+; RV32I-LABEL: muli64_p72:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li a2, 72
+; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: call __muldi3
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: muli64_p72:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a2, 72
+; RV32IM-NEXT: mul a1, a1, a2
+; RV32IM-NEXT: mulhu a3, a0, a2
+; RV32IM-NEXT: add a1, a3, a1
+; RV32IM-NEXT: mul a0, a0, a2
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli64_p72:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 72
+; RV64I-NEXT: tail __muldi3
+;
+; RV64IM-LABEL: muli64_p72:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 72
+; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i64 %a, 72
+ ret i64 %1
+}
define i32 @muli32_m63(i32 %a) nounwind {
; RV32I-LABEL: muli32_m63:
@@ -1327,10 +1453,10 @@ define i128 @muli128_m3840(i128 %a) nounwind {
; RV32I-NEXT: sltu a7, a5, a4
; RV32I-NEXT: sub a6, a6, t2
; RV32I-NEXT: mv t1, a7
-; RV32I-NEXT: beq t0, a3, .LBB36_2
+; RV32I-NEXT: beq t0, a3, .LBB40_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu t1, t0, a3
-; RV32I-NEXT: .LBB36_2:
+; RV32I-NEXT: .LBB40_2:
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: sub a1, t0, a3
; RV32I-NEXT: sub a5, a5, a4
@@ -1441,10 +1567,10 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32I-NEXT: sltu a7, a3, a6
; RV32I-NEXT: or t0, t0, a5
; RV32I-NEXT: mv a5, a7
-; RV32I-NEXT: beq a4, t0, .LBB37_2
+; RV32I-NEXT: beq a4, t0, .LBB41_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a5, a4, t0
-; RV32I-NEXT: .LBB37_2:
+; RV32I-NEXT: .LBB41_2:
; RV32I-NEXT: srli t1, a4, 26
; RV32I-NEXT: slli t2, a2, 6
; RV32I-NEXT: srli t3, a2, 26
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