[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Craig Topper via llvm-commits]

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@@ -70,10 +70,14 @@
 ///
 //===----------------------------------------------------------------------===//
 
-def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
+// VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
+// extended from the vector element size.
+def riscv_vmv_x_s : RVSDNode<"VMV_X_S",
                            SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,
                                                 SDTCisInt<1>]>>;
-def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB",
+
+// Read VLENB CSR
+def riscv_read_vlenb : RVSDNode<"READ_VLENB",
                               SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
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topperc wrote:

Identation

https://github.com/llvm/llvm-project/pull/138381