[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Craig Topper via llvm-commits]

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@@ -32,10 +32,11 @@ class RVInstRMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, RISCVOpcode opcod
   let Inst{25} = imm4{0};
 }
 
-def riscv_mopr  : SDNode<"RISCVISD::MOPR",
+// May-Be-Operations
+def riscv_mopr  : RVSDNode<"MOPR",
                          SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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topperc wrote:

Indentation

https://github.com/llvm/llvm-project/pull/138381