[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Sam Elliott via llvm-commits]

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@@ -14,6 +14,15 @@
 // RISC-V specific DAG Nodes.
 //===----------------------------------------------------------------------===//
 
+class RVSDNode<string opcode, SDTypeProfile type_profile,
+                list<SDNodeProperty> properties = []>
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lenary wrote:

Done

https://github.com/llvm/llvm-project/pull/138381