[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Craig Topper via llvm-commits]

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@@ -11,15 +11,48 @@
 
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 
+#define GET_SDNODE_ENUM
+#include "RISCVGenSDNodeInfo.inc"
+
 namespace llvm {
 
-class RISCVSelectionDAGInfo : public SelectionDAGTargetInfo {
+namespace RISCVISD {
+// RISCVISD Node TSFlags
+enum : unsigned {
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topperc wrote:

uint32_t

https://github.com/llvm/llvm-project/pull/138381