[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Craig Topper via llvm-commits]

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@@ -2835,7 +3000,10 @@ foreach vti = !listconcat(AllFloatVectors, AllBFloatVectors) in {
 // Miscellaneous RISCVISD SDNodes
 //===----------------------------------------------------------------------===//
 
-def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2,
+// Matches the semantics of the vid.v instruction, with a mask and VL
+// operand.
+let HasMaskOp = true in
+def riscv_vid_vl : RVSDNode<"VID_VL", SDTypeProfile<1, 2,
                           [SDTCisVec<0>, SDTCVecEltisVT<1, i1>,
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topperc wrote:

This should be intended farther unless it was to avoid a line wrap?

https://github.com/llvm/llvm-project/pull/138381