[llvm] [LV] Compute register usage for interleaving on VPlan. (PR #126437)

[Florian Hahn via llvm-commits]

https://github.com/fhahn commented:

> Hi @fhahn, we are seeing a perf regression(around ~7%) in a TSVC benchmark [s351](https://github.com/UoB-HPC/TSVC_2/blob/badf9adb2974867ac0937718d85a44dec6dec95a/src/tsvc.c#L2893) due to this change when compiled with `-Ofast` on a `neoverse-v2` machine.
> 
> From the [assembly](https://www.diffchecker.com/qyDFTd1u/) I can see there is less interleaving in the hot loop after this change, maybe that's causing the slowdown? How do you reckon we can go about fixing this?
> 
> Thanks!

@yashssh  thanks for the heads-up. Could you share a full reproducer with the LLVM IR before loop-vectorize?



https://github.com/llvm/llvm-project/pull/126437