[llvm] [RISCV] Remove`riscv.segN.load/store` in favor of their mask variants (PR #137045)

[Min-Yih Hsu via llvm-commits]

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@@ -23975,7 +23919,10 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
   // potentially under larger LMULs) because we checked that the fixed vector
   // type fits in isLegalInterleavedAccessType
   Value *VL = ConstantInt::get(XLenTy, VTy->getNumElements());
-  Ops.append({SI->getPointerOperand(), VL});
+  // All-ones mask.
+  Value *StoreMask = ConstantVector::getSplat(
+      VTy->getElementCount(), ConstantInt::getTrue(SVI->getContext()));
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mshockwave wrote:

oh right, I changed one placed but forgot about other occurrences. It's fixed now.

https://github.com/llvm/llvm-project/pull/137045