[llvm] [RISCV][MC] Add aliases for beq/bne with x0 as the first argument => beqz/bnez (PR #139086)

[Craig Topper via llvm-commits]

topperc wrote:

> Because we're mostly compiling with
RVC enabled, you only see the beq/bne forms with x0 as the first
operand in disassembly in the case of the second operand being a register that isn't
compressible.

c.beqz/c.bnez has a smaller displacement range too doesn't it?

https://github.com/llvm/llvm-project/pull/139086