[llvm] [AMDGPU] Rework GFX11 VALU Mask Write Hazard (PR #138663)

[Carl Ritson via llvm-commits]

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@@ -3044,9 +3044,8 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
     return false;
 
   const Register HazardReg = HazardDef->getReg();
-  auto *HazardRegRC = TRI->getPhysRegBaseClass(HazardReg);
-  bool IsSGPR32 = (HazardRegRC == TRI->getSGPRClassForBitWidth(32)) ||
-                  HazardReg == AMDGPU::VCC_LO || HazardReg == AMDGPU::VCC_HI;
+  bool IsSGPR32 = (AMDGPU::SReg_32RegClass.contains(HazardReg) ||
+                   HazardReg == AMDGPU::VCC_LO || HazardReg == AMDGPU::VCC_HI);
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perlfu wrote:

Thanks. My original method of accessing the RC didn't work for VCC.

https://github.com/llvm/llvm-project/pull/138663