[llvm] [AArch64] Stop reserved registers from being saved in prolog/epilog (PR #138448)

[Nuko Y. via llvm-commits]

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@@ -551,6 +563,11 @@ bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
   return getReservedRegs(MF)[Reg];
 }
 
+bool AArch64RegisterInfo::isUserReservedReg(const MachineFunction &MF,
+                                            MCRegister Reg) const {
+  return getUserReservedRegs(MF)[Reg];
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yasuna-oribe wrote:

I was fully aware of this when writing the function, but take a look at line 431, `// FIXME: avoid re-calculating this every time.` for getStrictlyPreservedRegs, a way more expensive function that is also called in the same loop.
The loop in determineCalleeSaves only loops over callee-saved regs (CSRegs) anyway, and if you insist, I can save the BitVector at the top of the function and lookup from it, but it will be inconsistent with the rest of the function that uses isReserved directly (which calls getPreservedRegs and then getStrictlyPreservedRegs), and I doubt it will make a difference.

https://github.com/llvm/llvm-project/pull/138448