[llvm] 6babd63 - [XCore] TableGen-erate SDNode descriptions (#138869)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 7 14:03:26 PDT 2025
Author: Sergei Barannikov
Date: 2025-05-08T00:03:23+03:00
New Revision: 6babd63a4bbc094bee4ef8e75f95dccd32325c15
URL: https://github.com/llvm/llvm-project/commit/6babd63a4bbc094bee4ef8e75f95dccd32325c15
DIFF: https://github.com/llvm/llvm-project/commit/6babd63a4bbc094bee4ef8e75f95dccd32325c15.diff
LOG: [XCore] TableGen-erate SDNode descriptions (#138869)
This consolidates node definitions into one place and enables automatic
node verification.
Part of #119709.
Added:
Modified:
llvm/lib/Target/XCore/CMakeLists.txt
llvm/lib/Target/XCore/XCoreISelLowering.cpp
llvm/lib/Target/XCore/XCoreISelLowering.h
llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/XCore/CMakeLists.txt b/llvm/lib/Target/XCore/CMakeLists.txt
index 447f5c5452885..f411c658b43b0 100644
--- a/llvm/lib/Target/XCore/CMakeLists.txt
+++ b/llvm/lib/Target/XCore/CMakeLists.txt
@@ -8,6 +8,7 @@ tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM XCoreGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(XCoreCommonTableGen)
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index ac199230b2c07..1c6e294597c34 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -40,33 +40,6 @@ using namespace llvm;
#define DEBUG_TYPE "xcore-lower"
-const char *XCoreTargetLowering::
-getTargetNodeName(unsigned Opcode) const
-{
- switch ((XCoreISD::NodeType)Opcode)
- {
- case XCoreISD::FIRST_NUMBER : break;
- case XCoreISD::BL : return "XCoreISD::BL";
- case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
- case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
- case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
- case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
- case XCoreISD::STWSP : return "XCoreISD::STWSP";
- case XCoreISD::RETSP : return "XCoreISD::RETSP";
- case XCoreISD::LADD : return "XCoreISD::LADD";
- case XCoreISD::LSUB : return "XCoreISD::LSUB";
- case XCoreISD::LMUL : return "XCoreISD::LMUL";
- case XCoreISD::MACCU : return "XCoreISD::MACCU";
- case XCoreISD::MACCS : return "XCoreISD::MACCS";
- case XCoreISD::CRC8 : return "XCoreISD::CRC8";
- case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
- case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
- case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
- case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
- }
- return nullptr;
-}
-
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
const XCoreSubtarget &Subtarget)
: TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h
index 1e036ea316978..bad6588cad740 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.h
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.h
@@ -23,65 +23,6 @@ namespace llvm {
// Forward delcarations
class XCoreSubtarget;
- namespace XCoreISD {
- enum NodeType : unsigned {
- // Start the numbering where the builtin ops and target ops leave off.
- FIRST_NUMBER = ISD::BUILTIN_OP_END,
-
- // Branch and link (call)
- BL,
-
- // pc relative address
- PCRelativeWrapper,
-
- // dp relative address
- DPRelativeWrapper,
-
- // cp relative address
- CPRelativeWrapper,
-
- // Load word from stack
- LDWSP,
-
- // Store word to stack
- STWSP,
-
- // Corresponds to retsp instruction
- RETSP,
-
- // Corresponds to LADD instruction
- LADD,
-
- // Corresponds to LSUB instruction
- LSUB,
-
- // Corresponds to LMUL instruction
- LMUL,
-
- // Corresponds to MACCU instruction
- MACCU,
-
- // Corresponds to MACCS instruction
- MACCS,
-
- // Corresponds to CRC8 instruction
- CRC8,
-
- // Jumptable branch.
- BR_JT,
-
- // Jumptable branch using long branches for each entry.
- BR_JT32,
-
- // Offset from frame pointer to the first (possible) on-stack argument
- FRAME_TO_ARGS_OFFSET,
-
- // Exception handler return. The stack is restored to the first
- // followed by a jump to the second argument.
- EH_RETURN,
- };
- }
-
//===--------------------------------------------------------------------===//
// TargetLowering Implementation
//===--------------------------------------------------------------------===//
@@ -109,10 +50,6 @@ namespace llvm {
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const override;
- /// getTargetNodeName - This method returns the name of a target specific
- // DAG node.
- const char *getTargetNodeName(unsigned Opcode) const override;
-
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override;
diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
index 0d097076348ca..bc34ab4319690 100644
--- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
@@ -10,11 +10,19 @@
//
//===----------------------------------------------------------------------===//
+#include "XCoreSelectionDAGInfo.h"
#include "XCoreTargetMachine.h"
+
+#define GET_SDNODE_DESC
+#include "XCoreGenSDNodeInfo.inc"
+
using namespace llvm;
#define DEBUG_TYPE "xcore-selectiondag-info"
+XCoreSelectionDAGInfo::XCoreSelectionDAGInfo()
+ : SelectionDAGGenTargetInfo(XCoreGenSDNodeInfo) {}
+
SDValue XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
index 2abf526779785..4a2848229aca9 100644
--- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
+++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
@@ -15,10 +15,15 @@
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#define GET_SDNODE_ENUM
+#include "XCoreGenSDNodeInfo.inc"
+
namespace llvm {
-class XCoreSelectionDAGInfo : public SelectionDAGTargetInfo {
+class XCoreSelectionDAGInfo : public SelectionDAGGenTargetInfo {
public:
+ XCoreSelectionDAGInfo();
+
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Op1, SDValue Op2,
SDValue Op3, Align Alignment, bool isVolatile,
@@ -27,6 +32,6 @@ class XCoreSelectionDAGInfo : public SelectionDAGTargetInfo {
MachinePointerInfo SrcPtrInfo) const override;
};
-}
+} // namespace llvm
#endif
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