[llvm] [GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (PR #138574)

[Chinmay Deshpande via llvm-commits]

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@@ -872,12 +872,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   // Report legal for any types we can handle anywhere. For the cases only legal
   // on the SALU, RegBankSelect will be able to re-legalize.
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
-    .legalFor({S32, S1, S64, V2S32, S16, V2S16, V4S16})
-    .clampScalar(0, S32, S64)
-    .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
-    .fewerElementsIf(vectorWiderThan(0, 64), fewerEltsToSize64Vector(0))
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chinmaydd wrote:

I dont believe so. 

A `2xi128` vector is wider than 64 bits which satisfies the predicate here. Once the `fewerElements` action is chosen, the mutation at [fewerEltsToSize64Vector](https://github.com/llvm/llvm-project/blob/0d0eed419fa362e1932b694e01534f4012dcea97/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp#L110) chooses a vector of type `0xs128` to break it down. This eventually causes an FPE in [LegalizerHelper](https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp#L62).

`fewerEltsToSize64Vector` was not written with vectors of element types wider than 64 bits.

https://github.com/llvm/llvm-project/pull/138574