[llvm] c3a638c - [GlobalISel] Fix silently dropped MIFlags on selected instructions (#138851)

[via llvm-commits]

Author: Pierre van Houtryve
Date: 2025-05-07T14:07:16+02:00
New Revision: c3a638caabf96fedce09f4b58b4ba550a015e150

URL: https://github.com/llvm/llvm-project/commit/c3a638caabf96fedce09f4b58b4ba550a015e150
DIFF: https://github.com/llvm/llvm-project/commit/c3a638caabf96fedce09f4b58b4ba550a015e150.diff

LOG: [GlobalISel] Fix silently dropped MIFlags on selected instructions (#138851)

We used uint16 for flags but flags now go up to 24 bits, so all flags in bits 16-24 were lost.

Fixes #110801

Added: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index 654112e86e873..6c4f03649149e 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -61,7 +61,7 @@ bool GIMatchTableExecutor::executeMatchTable(
   // Bypass the flag check on the instruction, and only look at the MCInstrDesc.
   bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
 
-  const uint16_t Flags = State.MIs[0]->getFlags();
+  const uint32_t Flags = State.MIs[0]->getFlags();
 
   enum RejectAction { RejectAndGiveUp, RejectAndResume };
   auto handleReject = [&]() -> RejectAction {
@@ -80,7 +80,7 @@ bool GIMatchTableExecutor::executeMatchTable(
     for (auto MIB : OutMIs) {
       // Set the NoFPExcept flag when no original matched instruction could
       // raise an FP exception, but the new instruction potentially might.
-      uint16_t MIBFlags = Flags | MIB.getInstr()->getFlags();
+      uint32_t MIBFlags = Flags | MIB.getInstr()->getFlags();
       if (NoFPException && MIB->mayRaiseFPException())
         MIBFlags |= MachineInstr::NoFPExcept;
       if (Observer)

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
new file mode 100644
index 0000000000000..c87284fade303
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-- -run-pass=instruction-select -o - %s | FileCheck %s
+
+# Checks MI Flags are preserved on selected instructions.
+
+---
+name:            s_or_i32_disjoint
+tracksRegLiveness: true
+regBankSelected: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+
+    ; CHECK-LABEL: name: s_or_i32_disjoint
+    ; CHECK: liveins: $sgpr0, $sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = disjoint S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
+    ; CHECK-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
+    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s32) = disjoint G_OR %0, %1
+    $sgpr0 = COPY %2
+    SI_RETURN_TO_EPILOG implicit $sgpr0
+...