[llvm] [AArch64][SVE] Add patterns for bit-select instructions. (PR #138689)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

> If agreeable I think now is the time for a bit of refactoring. Given `AArch64ISD::BSP` exists, what do you think to the idea of extending `performIntrinsicCombine` to lower `int_aarch64_sve_bsl`, `int_aarch64_sve_bsl1n`, `int_aarch64_sve_bsl2n` and `int_aarch64_sve_nbsl` to use `AArch64ISD::BSP`? That will reduce the number of patterns required for selection whilst meaning the intrinsics can benefit from any potential combines involving `AArch64ISD::BSP`. Given at worst the intrinsics lower to `AArch64ISD::BSP` and a `NOT` I don't think we risk not being able to reconstitute the original input.

I think that sounds like a good idea. I suppose the other option would be to lower the intrinsics to elementary IR in `instCombineIntrinsic`, but as you say it may be too difficult to reconstitute the BSL patterns reliably later on.

Would you like me to add the lowering to `AArch64ISD::BSP` here or in a separate PR?

https://github.com/llvm/llvm-project/pull/138689