[llvm] [AArch64][SVE] Add patterns for bit-select instructions. (PR #138689)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

If agreeable I think now is the time for a bit of refactoring.  Given `AArch64ISD::BSP` exists what do you think to the idea of extending `performIntrinsicCombine` to lower `int_aarch64_sve_bsl`, `int_aarch64_sve_bsl1n`, `int_aarch64_sve_bsl2n` and `int_aarch64_sve_nbsl` to use `AArch64ISD::BSP`? That will reduce the number of patterns required for selection whilst meaning the intrinsics can benefit from any potential combines involving `AArch64ISD::BSP`.  Given at worst the intrinsics lower to `AArch64ISD::BSP` and a `NOT` I don't think we risk not being able to reconstitute the original input.

https://github.com/llvm/llvm-project/pull/138689