[llvm] Add support for intrinsic @llvm.frexp (PR #135774)
VISHAKH PRAKASH via llvm-commits
llvm-commits at lists.llvm.org
Wed May 7 00:34:03 PDT 2025
https://github.com/VishMCW updated https://github.com/llvm/llvm-project/pull/135774
>From a8dacb4ef003bf1fead4bde2cee2069dba88c13e Mon Sep 17 00:00:00 2001
From: VishMCW <vishakh.prakash at multicorewareinc.com>
Date: Wed, 7 May 2025 10:32:58 +0530
Subject: [PATCH] FEAT: add support for intrinsic @llvm.frexp.*
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 75 ++++++++++
llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 5 +
.../CodeGen/SPIRV/llvm-intrinsics/frexp.ll | 128 ++++++++++++++++++
3 files changed, 208 insertions(+)
create mode 100644 llvm/test/CodeGen/SPIRV/llvm-intrinsics/frexp.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 0db60c068bdff..2aa9fd8b6fd6d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -276,6 +276,12 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I, const ExtInstList &ExtInsts) const;
+ bool selectExtInstFREXP(Register ResVReg, const SPIRVType *ResType,
+ MachineInstr &I, CL::OpenCLExtInst CLInst,
+ GL::GLSLExtInst GLInst) const;
+ bool selectExtInstFREXP(Register ResVReg, const SPIRVType *ResType,
+ MachineInstr &I, const ExtInstList &ExtInsts) const;
+
bool selectLog10(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
@@ -765,6 +771,9 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
case TargetOpcode::G_FNEARBYINT:
return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
+ case TargetOpcode::G_FFREXP:
+ return selectExtInstFREXP(ResVReg, ResType, I, CL::frexp, GL::Frexp);
+
case TargetOpcode::G_SMULH:
return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi);
case TargetOpcode::G_UMULH:
@@ -1018,6 +1027,72 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
return false;
}
+bool SPIRVInstructionSelector::selectExtInstFREXP(
+ Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
+ CL::OpenCLExtInst CLInst, GL::GLSLExtInst GLInst) const {
+ ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CLInst},
+ {SPIRV::InstructionSet::GLSL_std_450, GLInst}};
+ return selectExtInstFREXP(ResVReg, ResType, I, ExtInsts);
+}
+
+bool SPIRVInstructionSelector::selectExtInstFREXP(
+ Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
+ const ExtInstList &ExtInsts) const {
+
+ for (const auto &Ex : ExtInsts) {
+ SPIRV::InstructionSet::InstructionSet Set = Ex.first;
+ uint32_t Opcode = Ex.second;
+ if (!STI.canUseExtInstSet(Set))
+ continue;
+ Type *ResTy = nullptr;
+ StringRef ResName;
+
+ if (!GR.findValueAttrs(&I, ResTy, ResName))
+ report_fatal_error("Not enough info to select the frexp instruction");
+ if (!ResTy || !ResTy->isStructTy())
+ report_fatal_error("Expect struct type result for frexp instruction");
+
+ MachineIRBuilder MIRBuilder(I);
+ SPIRVType *PointeeTy = GR.getSPIRVTypeForVReg(I.getOperand(1).getReg());
+ assert((PointeeTy->getOpcode() == SPIRV::OpTypeVector ||
+ PointeeTy->getOpcode() == SPIRV::OpTypeInt) &&
+ "Expected integer or vector type for second operand");
+
+ const SPIRVType *PointerType = GR.getOrCreateSPIRVPointerType(
+ PointeeTy, MIRBuilder, SPIRV::StorageClass::Function);
+ Register PointerVReg =
+ createVirtualRegister(PointerType, &GR, MRI, MRI->getMF());
+
+ auto It = getOpVariableMBBIt(I);
+ auto MIB = BuildMI(*It->getParent(), It, It->getDebugLoc(),
+ TII.get(SPIRV::OpVariable))
+ .addDef(PointerVReg)
+ .addUse(GR.getSPIRVTypeID(PointerType))
+ .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function))
+ .constrainAllUses(TII, TRI, RBI);
+
+ MIB = MIB &
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(
+ GR.getSPIRVTypeForVReg(I.getOperand(2).getReg())))
+ .addImm(static_cast<uint32_t>(Ex.first))
+ .addImm(Opcode)
+ .add(I.getOperand(2))
+ .addUse(PointerVReg)
+ .constrainAllUses(TII, TRI, RBI);
+
+ MIB = MIB &
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
+ .addDef(I.getOperand(1).getReg())
+ .addUse(GR.getSPIRVTypeID(PointeeTy))
+ .addUse(PointerVReg)
+ .constrainAllUses(TII, TRI, RBI);
+ return MIB;
+ }
+ return false;
+}
+
bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
const SPIRVType *ResType,
MachineInstr &I,
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index 578e82881f6e8..638e901fe9d2c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -209,6 +209,11 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
.legalForCartesianProduct(allIntScalarsAndVectors)
.legalIf(extendedScalarsAndVectorsProduct);
+ getActionDefinitionsBuilder(G_FFREXP)
+ .legalForCartesianProduct(allFloatScalarsAndVectors,
+ {s32, v2s32, v3s32, v4s32, v8s32, v16s32})
+ .clampScalar(1, s32, s32);
+
// Extensions.
getActionDefinitionsBuilder({G_TRUNC, G_ZEXT, G_SEXT, G_ANYEXT})
.legalForCartesianProduct(allScalarsAndVectors)
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/frexp.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/frexp.ll
new file mode 100644
index 0000000000000..68cc5bd2b59b0
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/frexp.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+
+; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std"
+; CHECK: %[[#float_32_type:]] = OpTypeFloat 32
+; CHECK: %[[#int_32_type:]] = OpTypeInt 32 0
+; CHECK: %[[#fn_ptr_type_i32:]] = OpTypePointer Function %[[#int_32_type]]
+; CHECK: %[[#const_negzero:]] = OpConstant %[[#float_32_type]] -0
+; CHECK: %[[#float_64_type:]] = OpTypeFloat 64
+; CHECK: %[[#undef_double:]] = OpUndef %[[#float_64_type]]
+; CHECK: %[[#vec2_float_type:]] = OpTypeVector %[[#float_32_type]] 2
+; CHECK: %[[#vec2_int_type:]] = OpTypeVector %[[#int_32_type]] 2
+; CHECK: %[[#fn_ptr_type_vec2_i32:]] = OpTypePointer Function %[[#vec2_int_type]]
+; CHECK: %[[#vec2_null:]] = OpConstantNull %[[#vec2_float_type]]
+; CHECK: %[[#scalar_null:]] = OpConstantNull %[[#float_32_type]]
+; CHECK: %[[#const_composite1:]] = OpConstantComposite %[[#vec2_float_type]] %[[#scalar_null]] %[[#const_negzero]]
+; CHECK: %[[#vec4_float_type:]] = OpTypeVector %[[#float_32_type]] 4
+; CHECK: %[[#vec4_int_type:]] = OpTypeVector %[[#int_32_type]] 4
+; CHECK: %[[#fn_ptr_type_vec4_i32:]] = OpTypePointer Function %[[#vec4_int_type]]
+; CHECK: %[[#undef_float:]] = OpUndef %[[#float_32_type]]
+; CHECK: %[[#spec_const_op:]] = OpSpecConstantOp %[[#float_32_type]] 124 %[[#undef_float]]
+; CHECK: %[[#const_composite2:]] = OpConstantComposite %[[#vec4_float_type]] %[[#const_16:]] %[[#const_neg32:]] %[[#spec_const_op]] %[[#const_9999:]]
+; CHECK: %[[#vec2_double_type:]] = OpTypeVector %[[#float_64_type]] 2
+
+; CHECK: %[[#]] = OpFunctionParameter %[[#float_32_type]]
+; CHECK: %[[#var1:]] = OpVariable %[[#fn_ptr_type_i32]] Function
+; CHECK: %[[#extinst1:]] = OpExtInst %[[#float_32_type]] %[[#extinst_id]] frexp %[[#const_negzero]] %[[#var1]]
+; CHECK: %[[#exp_part_var:]] = OpLoad %[[#int_32_type]] %[[#var1]]
+; CHECK: OpReturnValue %[[#exp_part_var]]
+define i32 @frexp_negzero(float %x) {
+ %ret = call { float, i32 } @llvm.frexp.f32.i32(float -0.0)
+ %f_part = extractvalue { float, i32 } %ret, 0
+ %exp_part = extractvalue { float, i32 } %ret, 1
+ ret i32 %exp_part
+}
+
+; CHECK: %[[#var2:]] = OpVariable %[[#fn_ptr_type_i32]] Function
+; CHECK: %[[#extinst2:]] = OpExtInst %[[#float_64_type]] %[[#extinst_id]] frexp %[[#undef_double]] %[[#var2]]
+; CHECK: %[[#f_part_var:]] = OpLoad %[[#int_32_type]] %[[#var2]]
+; CHECK: OpReturnValue %[[#extinst2]]
+define double @frexp_undef() {
+ %ret = call { double, i32 } @llvm.frexp.f64.i32(double undef)
+ %f_part = extractvalue { double, i32 } %ret, 0
+ %exp_part = extractvalue { double, i32 } %ret, 1
+ ret double %f_part
+}
+
+; CHECK: %[[#x_var4:]] = OpFunctionParameter %[[#float_32_type]]
+; CHECK: %[[#var10:]] = OpVariable %[[#fn_ptr_type_i32]] Function
+; CHECK: %[[#extinst10:]] = OpExtInst %[[#float_32_type]] %[[#extinst_id]] frexp %[[#x_var4]] %[[#var10]]
+; CHECK: %[[#exp_part_var2:]] = OpLoad %[[#int_32_type]] %[[#var10]]
+; CHECK: OpReturnValue %[[#exp_part_var2]]
+define i32 @frexp_frexp_get_int(float %x) {
+ %frexp0 = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %f_part = extractvalue { float, i32 } %frexp0, 0
+ %exp_part = extractvalue { float, i32 } %frexp0, 1
+ ret i32 %exp_part
+}
+
+; CHECK: %[[#var3:]] = OpVariable %[[#fn_ptr_type_vec2_i32]] Function
+; CHECK: %[[#extinst3:]] = OpExtInst %[[#vec2_float_type]] %[[#extinst_id]] frexp %[[#vec2_null]] %[[#var3]]
+; CHECK: %[[#f_part_var2:]] = OpLoad %[[#vec2_int_type]] %[[#var3]]
+; CHECK: OpReturnValue %[[#extinst3]]
+define <2 x float> @frexp_zero_vector() {
+ %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> zeroinitializer)
+ %f_part = extractvalue { <2 x float>, <2 x i32> } %ret, 0
+ %exp_part = extractvalue { <2 x float>, <2 x i32> } %ret, 1
+ ret <2 x float> %f_part
+}
+
+; CHECK: %[[#var4:]] = OpVariable %[[#fn_ptr_type_vec2_i32]] Function
+; CHECK: %[[#extinst4:]] = OpExtInst %[[#vec2_float_type]] %[[#extinst_id]] frexp %[[#const_composite1]] %[[#var4]]
+; CHECK: %[[#f_part_var3:]] = OpLoad %[[#vec2_int_type]] %[[#var4]]
+; CHECK: OpReturnValue %[[#extinst4]]
+define <2 x float> @frexp_zero_negzero_vector() {
+ %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0.0, float -0.0>)
+ %f_part = extractvalue { <2 x float>, <2 x i32> } %ret, 0
+ %exp_part = extractvalue { <2 x float>, <2 x i32> } %ret, 1
+ ret <2 x float> %f_part
+}
+
+; CHECK: %[[#var5:]] = OpVariable %[[#fn_ptr_type_vec4_i32]] Function
+; CHECK: %[[#extinst5:]] = OpExtInst %[[#vec4_float_type]] %[[#extinst_id]] frexp %[[#const_composite2]] %[[#var5]]
+; CHECK: %[[#f_part_var4:]] = OpLoad %[[#vec4_int_type]] %[[#var5]]
+; CHECK: OpReturnValue %[[#extinst5]]
+define <4 x float> @frexp_nonsplat_vector() {
+ %ret = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> <float 16.0, float -32.0, float undef, float 9999.0>)
+ %f_part = extractvalue { <4 x float>, <4 x i32> } %ret, 0
+ %exp_part = extractvalue { <4 x float>, <4 x i32> } %ret, 1
+ ret <4 x float> %f_part
+}
+
+; CHECK: %[[#x_var2:]] = OpFunctionParameter %[[#float_32_type]]
+; CHECK: %[[#var6:]] = OpVariable %[[#fn_ptr_type_i32]] Function
+; CHECK: %[[#var7:]] = OpVariable %[[#fn_ptr_type_i32]] Function
+; CHECK: %[[#extinst6:]] = OpExtInst %[[#float_32_type]] %[[#extinst_id]] frexp %[[#x_var2]] %[[#var6]]
+; CHECK: %[[#load1:]] = OpLoad %[[#int_32_type]] %[[#var6]]
+; CHECK: %[[#extinst7:]] = OpExtInst %[[#float_32_type]] %[[#extinst_id]] frexp %[[#extinst6]] %[[#var7]]
+; CHECK: %[[#f_part_var5:]] = OpLoad %[[#int_32_type]] %[[#var7]]
+; CHECK: OpReturnValue %[[#extinst7]]
+define float @frexp_frexp(float %x) {
+ %frexp0 = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %frexp0_f_part = extractvalue { float, i32 } %frexp0, 0
+ %frexp0_exp_part = extractvalue { float, i32 } %frexp0, 1
+ %frexp1 = call { float, i32 } @llvm.frexp.f32.i32(float %frexp0_f_part)
+ %frexp1_f_part = extractvalue { float, i32 } %frexp1, 0
+ %frexp1_exp_part = extractvalue { float, i32 } %frexp1, 1
+ ret float %frexp1_f_part
+}
+
+; CHECK: %[[#x_var3:]] = OpFunctionParameter %[[#vec2_double_type]]
+; CHECK: %[[#var9:]] = OpVariable %[[#fn_ptr_type_vec2_i32]] Function
+; CHECK: %[[#extinst9:]] = OpExtInst %[[#vec2_double_type]] %[[#extinst_id]] frexp %[[#x_var3]] %[[#var9]]
+; CHECK: %[[#f_part_var6:]] = OpLoad %[[#vec2_int_type]] %[[#var9]]
+; CHECK: OpReturnValue %[[#extinst9]]
+define <2 x double> @frexp_frexp_vector(<2 x double> %x) {
+ %frexp0 = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %x)
+ %f_part = extractvalue { <2 x double>, <2 x i32> } %frexp0, 0
+ %exp_part = extractvalue { <2 x double>, <2 x i32> } %frexp0, 1
+ ret <2 x double> %f_part
+}
+
+declare { float, i32 } @llvm.frexp.f32.i32(float)
+declare { double, i32 } @llvm.frexp.f64.i32(double)
+declare { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float>)
+declare { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float>)
+declare { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double>)
+declare { float, i8 } @llvm.frexp.f32.i8(float)
+
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