[llvm] [DAGCombiner] Fold pattern for srl-shl-zext (PR #138290)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b1b5c5335..8469b2952 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10994,10 +10994,9 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
             ZExt.getValueType().getScalarSizeInBits() -
             ZExt.getOperand(0).getValueType().getScalarSizeInBits();
         if (N1C->getZExtValue() <= NumLeadingZeros) {
-          return DAG.getNode(
-              N0.getOpcode(), SDLoc(N0), VT,
-              DAG.getNode(ISD::SRL, SDLoc(N0), VT, Other, N1),
-              ZExt);
+          return DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
+                             DAG.getNode(ISD::SRL, SDLoc(N0), VT, Other, N1),
+                             ZExt);
         }
       }
     }

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https://github.com/llvm/llvm-project/pull/138290