[llvm] 4eac576 - [RISCV] Add scheduler definitions for SpacemiT-X60 (#137343)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 6 09:31:01 PDT 2025
Author: Mikhail R. Gadelha
Date: 2025-05-06T13:30:57-03:00
New Revision: 4eac576654d857e2d8d59783b7eb2d70cb0675f9
URL: https://github.com/llvm/llvm-project/commit/4eac576654d857e2d8d59783b7eb2d70cb0675f9
DIFF: https://github.com/llvm/llvm-project/commit/4eac576654d857e2d8d59783b7eb2d70cb0675f9.diff
LOG: [RISCV] Add scheduler definitions for SpacemiT-X60 (#137343)
This patch adds an initial scheduler model for the SpacemiT-X60,
including latency for scalar instructions only.
The scheduler is based on the documented characteristics of the C908,
which the SpacemiT-X60 is believed to be based on, and provides the
expected latency for several instructions. I ran a probe to confirm all
of these values and to get the latency of instructions not provided by
the C908 documentation (e.g., double floating-point instructions).
For load and store instructions, the C908 documentation says the latency
is \>= 3 for load and 1 for store. I tried a few combinations of values
until I got the current values of 5 and 3, which yield the best results.
Although the X60 does appear to support multiple issue for at least some
floating point instructions, this model assumes single issue as
increasing it reduces the gains below.
This patch gives a geomean improvement of ~4% on SPEC CPU 2017 for both
rva22u64 and rva22u64_v, with some benchmarks improving up to 18%
(508.namd_r). There were a couple of execution time regressions, but
only in noisy benchmarks (523.xalancbmk_r and 510.parest_r).
* rva22u64: https://lnt.lukelau.me/db_default/v4/nts/507?compare_to=405
(compares a55f7275 to the baseline 8286b804)
* rva22u64_v:
https://lnt.lukelau.me/db_default/v4/nts/474?compare_to=404 (compares
a55f7275 to the baseline 8286b804)
This initial scheduling model is strongly focused on providing
sufficient definitions to provide improved performance for the
SpacemiT-X60. Further incremental gains may be possible through a much
more detailed microarchitectural analysis, but that is left to future
work.
Further scheduling definitions for RVV can be added in a future PR.
Added:
llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
Modified:
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 6ecf6460d1e32..7f96c6718ffa9 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -58,6 +58,7 @@ include "RISCVSchedSiFive7.td"
include "RISCVSchedSiFiveP400.td"
include "RISCVSchedSiFiveP500.td"
include "RISCVSchedSiFiveP600.td"
+include "RISCVSchedSpacemitX60.td"
include "RISCVSchedSyntacoreSCR1.td"
include "RISCVSchedSyntacoreSCR345.td"
include "RISCVSchedSyntacoreSCR7.td"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 9e5b586a53d3f..db57f5c4da24e 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -608,7 +608,7 @@ def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
TuneShiftedZExtWFusion]>;
def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
- NoSchedModel,
+ SpacemitX60Model,
!listconcat(RVA22S64Features,
[FeatureStdExtV,
FeatureStdExtSscofpmf,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
new file mode 100644
index 0000000000000..c21ab969d12ac
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -0,0 +1,353 @@
+//=- RISCVSchedSpacemitX60.td - Spacemit X60 Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// Scheduler model for the SpacemiT-X60 processor based on documentation of the
+// C908 and experiments on real hardware (bpi-f3).
+//
+//===----------------------------------------------------------------------===//
+
+def SpacemitX60Model : SchedMachineModel {
+ let IssueWidth = 2; // dual-issue
+ let MicroOpBufferSize = 0; // in-order
+ let LoadLatency = 5; // worse case: >= 3
+ let MispredictPenalty = 9; // nine-stage
+
+ let CompleteModel = 0;
+
+ let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr];
+}
+
+let SchedModel = SpacemitX60Model in {
+
+//===----------------------------------------------------------------------===//
+// Define processor resources for Spacemit-X60
+
+// Information gathered from the C908 user manual:
+let BufferSize = 0 in {
+ // The LSU supports dual issue for scalar store/load instructions
+ def SMX60_LS : ProcResource<2>;
+
+ // An IEU can decode and issue two instructions at the same time
+ def SMX60_IEUA : ProcResource<1>;
+ def SMX60_IEUB : ProcResource<1>;
+ def SMX60_IEU : ProcResGroup<[SMX60_IEUA, SMX60_IEUB]>;
+
+ // Although the X60 does appear to support multiple issue for at least some
+ // floating point instructions, this model assumes single issue as
+ // increasing it reduces the gains we saw in performance
+ def SMX60_FP : ProcResource<1>;
+}
+
+//===----------------------------------------------------------------------===//
+
+// Branching
+def : WriteRes<WriteJmp, [SMX60_IEUA]>;
+def : WriteRes<WriteJal, [SMX60_IEUA]>;
+def : WriteRes<WriteJalr, [SMX60_IEUA]>;
+
+// Integer arithmetic and logic
+// Latency of ALU instructions is 1, but add.uw is 2
+def : WriteRes<WriteIALU32, [SMX60_IEU]>;
+def : WriteRes<WriteIALU, [SMX60_IEU]>;
+def : WriteRes<WriteShiftImm32, [SMX60_IEU]>;
+def : WriteRes<WriteShiftImm, [SMX60_IEU]>;
+def : WriteRes<WriteShiftReg32, [SMX60_IEU]>;
+def : WriteRes<WriteShiftReg, [SMX60_IEU]>;
+
+// Integer multiplication
+def : WriteRes<WriteIMul32, [SMX60_IEU]> { let Latency = 3; }
+
+// The latency of mul is 5, while in mulh, mulhsu, mulhu is 6
+// Worst case latency is used
+def : WriteRes<WriteIMul, [SMX60_IEU]> { let Latency = 6; }
+
+// Integer division/remainder
+// TODO: Latency set based on C908 datasheet and hasn't been
+// confirmed experimentally.
+let Latency = 12, ReleaseAtCycles = [12] in {
+ def : WriteRes<WriteIDiv32, [SMX60_IEUA]>;
+ def : WriteRes<WriteIRem32, [SMX60_IEUA]>;
+}
+let Latency = 20, ReleaseAtCycles = [20] in {
+ def : WriteRes<WriteIDiv, [SMX60_IEUA]>;
+ def : WriteRes<WriteIRem, [SMX60_IEUA]>;
+}
+
+// Bitmanip
+def : WriteRes<WriteRotateImm, [SMX60_IEU]>;
+def : WriteRes<WriteRotateImm32, [SMX60_IEU]>;
+def : WriteRes<WriteRotateReg, [SMX60_IEU]>;
+def : WriteRes<WriteRotateReg32, [SMX60_IEU]>;
+
+def : WriteRes<WriteCLZ, [SMX60_IEU]>;
+def : WriteRes<WriteCLZ32, [SMX60_IEU]>;
+def : WriteRes<WriteCTZ, [SMX60_IEU]>;
+def : WriteRes<WriteCTZ32, [SMX60_IEU]>;
+
+let Latency = 2 in {
+ def : WriteRes<WriteCPOP, [SMX60_IEU]>;
+ def : WriteRes<WriteCPOP32, [SMX60_IEU]>;
+}
+
+def : WriteRes<WriteORCB, [SMX60_IEU]>;
+def : WriteRes<WriteIMinMax, [SMX60_IEU]>;
+def : WriteRes<WriteREV8, [SMX60_IEU]>;
+
+let Latency = 2 in {
+ def : WriteRes<WriteSHXADD, [SMX60_IEU]>;
+ def : WriteRes<WriteSHXADD32, [SMX60_IEU]>;
+ def : WriteRes<WriteCLMUL, [SMX60_IEU]>;
+}
+
+// Single-bit instructions
+def : WriteRes<WriteSingleBit, [SMX60_IEU]>;
+def : WriteRes<WriteSingleBitImm, [SMX60_IEU]>;
+def : WriteRes<WriteBEXT, [SMX60_IEU]>;
+def : WriteRes<WriteBEXTI, [SMX60_IEU]>;
+
+// Memory/Atomic memory
+let Latency = 3 in {
+ def : WriteRes<WriteSTB, [SMX60_LS]>;
+ def : WriteRes<WriteSTH, [SMX60_LS]>;
+ def : WriteRes<WriteSTW, [SMX60_LS]>;
+ def : WriteRes<WriteSTD, [SMX60_LS]>;
+ def : WriteRes<WriteFST16, [SMX60_LS]>;
+ def : WriteRes<WriteFST32, [SMX60_LS]>;
+ def : WriteRes<WriteFST64, [SMX60_LS]>;
+ def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;
+ def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;
+}
+
+let Latency = 5 in {
+ def : WriteRes<WriteLDB, [SMX60_LS]>;
+ def : WriteRes<WriteLDH, [SMX60_LS]>;
+ def : WriteRes<WriteLDW, [SMX60_LS]>;
+ def : WriteRes<WriteLDD, [SMX60_LS]>;
+ def : WriteRes<WriteFLD16, [SMX60_LS]>;
+ def : WriteRes<WriteFLD32, [SMX60_LS]>;
+ def : WriteRes<WriteFLD64, [SMX60_LS]>;
+}
+
+// Atomics
+let Latency = 5 in {
+ def : WriteRes<WriteAtomicLDW, [SMX60_LS]>;
+ def : WriteRes<WriteAtomicLDD, [SMX60_LS]>;
+ def : WriteRes<WriteAtomicW, [SMX60_LS]>;
+ def : WriteRes<WriteAtomicD, [SMX60_LS]>;
+}
+
+// Floating point units Half precision
+let Latency = 4 in {
+ def : WriteRes<WriteFAdd16, [SMX60_FP]>;
+ def : WriteRes<WriteFMul16, [SMX60_FP]>;
+ def : WriteRes<WriteFSGNJ16, [SMX60_FP]>;
+ def : WriteRes<WriteFMinMax16, [SMX60_FP]>;
+}
+def : WriteRes<WriteFMA16, [SMX60_FP]> { let Latency = 5; }
+
+let Latency = 12, ReleaseAtCycles = [12] in {
+ def : WriteRes<WriteFDiv16, [SMX60_FP]>;
+ def : WriteRes<WriteFSqrt16, [SMX60_FP]>;
+}
+
+// Single precision
+let Latency = 4 in {
+ def : WriteRes<WriteFAdd32, [SMX60_FP]>;
+ def : WriteRes<WriteFMul32, [SMX60_FP]>;
+ def : WriteRes<WriteFSGNJ32, [SMX60_FP]>;
+ def : WriteRes<WriteFMinMax32, [SMX60_FP]>;
+}
+def : WriteRes<WriteFMA32, [SMX60_FP]> { let Latency = 5; }
+
+let Latency = 15, ReleaseAtCycles = [15] in {
+ def : WriteRes<WriteFDiv32, [SMX60_FP]>;
+ def : WriteRes<WriteFSqrt32, [SMX60_FP]>;
+}
+
+// Double precision
+let Latency = 5 in {
+ def : WriteRes<WriteFAdd64, [SMX60_FP]>;
+ def : WriteRes<WriteFMul64, [SMX60_FP]>;
+ def : WriteRes<WriteFSGNJ64, [SMX60_FP]>;
+}
+def : WriteRes<WriteFMinMax64, [SMX60_FP]> { let Latency = 4; }
+def : WriteRes<WriteFMA64, [SMX60_FP]> { let Latency = 6; }
+
+let Latency = 22, ReleaseAtCycles = [22] in {
+ def : WriteRes<WriteFDiv64, [SMX60_FP]>;
+ def : WriteRes<WriteFSqrt64, [SMX60_FP]>;
+}
+
+// Conversions
+let Latency = 6 in {
+ def : WriteRes<WriteFCvtF16ToI32, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtF32ToI32, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtF32ToI64, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtF64ToI64, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtF64ToI32, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtF16ToI64, [SMX60_IEU]>;
+}
+
+let Latency = 4 in {
+ def : WriteRes<WriteFCvtI32ToF16, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtI32ToF32, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtI32ToF64, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtI64ToF16, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtI64ToF32, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtI64ToF64, [SMX60_IEU]>;
+ def : WriteRes<WriteFCvtF16ToF32, [SMX60_FP]>;
+ def : WriteRes<WriteFCvtF16ToF64, [SMX60_FP]>;
+ def : WriteRes<WriteFCvtF32ToF16, [SMX60_FP]>;
+ def : WriteRes<WriteFCvtF32ToF64, [SMX60_FP]>;
+ def : WriteRes<WriteFCvtF64ToF16, [SMX60_FP]>;
+ def : WriteRes<WriteFCvtF64ToF32, [SMX60_FP]>;
+}
+
+let Latency = 6 in {
+ def : WriteRes<WriteFClass16, [SMX60_FP]>;
+ def : WriteRes<WriteFClass32, [SMX60_FP]>;
+ def : WriteRes<WriteFClass64, [SMX60_FP]>;
+
+ def : WriteRes<WriteFCmp16, [SMX60_FP]>;
+ def : WriteRes<WriteFCmp32, [SMX60_FP]>;
+ def : WriteRes<WriteFCmp64, [SMX60_FP]>;
+
+ def : WriteRes<WriteFMovF32ToI32, [SMX60_IEU]>;
+ def : WriteRes<WriteFMovF16ToI16, [SMX60_IEU]>;
+}
+
+let Latency = 4 in {
+ def : WriteRes<WriteFMovI16ToF16, [SMX60_IEU]>;
+ def : WriteRes<WriteFMovF64ToI64, [SMX60_IEU]>;
+ def : WriteRes<WriteFMovI64ToF64, [SMX60_IEU]>;
+ def : WriteRes<WriteFMovI32ToF32, [SMX60_IEU]>;
+}
+
+// Others
+def : WriteRes<WriteCSR, [SMX60_IEU]>;
+def : WriteRes<WriteNop, [SMX60_IEU]>;
+
+//===----------------------------------------------------------------------===//
+// Bypass and advance
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShiftImm, 0>;
+def : ReadAdvance<ReadShiftImm32, 0>;
+def : ReadAdvance<ReadShiftReg, 0>;
+def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd16, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul16, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
+def : ReadAdvance<ReadFMA16Addend, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA32Addend, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFMA64Addend, 0>;
+def : ReadAdvance<ReadFDiv16, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt16, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp16, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ16, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax16, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF16ToI32, 0>;
+def : ReadAdvance<ReadFCvtF16ToI64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF16, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF16, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFCvtF16ToF32, 0>;
+def : ReadAdvance<ReadFCvtF32ToF16, 0>;
+def : ReadAdvance<ReadFCvtF16ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF16, 0>;
+def : ReadAdvance<ReadFMovF16ToI16, 0>;
+def : ReadAdvance<ReadFMovI16ToF16, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass16, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+// Bitmanip
+def : ReadAdvance<ReadRotateImm, 0>;
+def : ReadAdvance<ReadRotateImm32, 0>;
+def : ReadAdvance<ReadRotateReg, 0>;
+def : ReadAdvance<ReadRotateReg32, 0>;
+def : ReadAdvance<ReadCLZ, 0>;
+def : ReadAdvance<ReadCLZ32, 0>;
+def : ReadAdvance<ReadCTZ, 0>;
+def : ReadAdvance<ReadCTZ32, 0>;
+def : ReadAdvance<ReadCPOP, 0>;
+def : ReadAdvance<ReadCPOP32, 0>;
+def : ReadAdvance<ReadORCB, 0>;
+def : ReadAdvance<ReadIMinMax, 0>;
+def : ReadAdvance<ReadREV8, 0>;
+def : ReadAdvance<ReadSHXADD, 0>;
+def : ReadAdvance<ReadSHXADD32, 0>;
+def : ReadAdvance<ReadCLMUL, 0>;
+// Single-bit instructions
+def : ReadAdvance<ReadSingleBit, 0>;
+def : ReadAdvance<ReadSingleBitImm, 0>;
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedV;
+defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedZabha;
+defm : UnsupportedSchedZbkb;
+defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedZfa;
+defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedSFB;
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
index 75f4b977a98b0..08cab7cd359b9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
@@ -302,33 +302,33 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV64X60-NEXT: .cfi_offset s4, -40
; RV64X60-NEXT: li t0, 0
; RV64X60-NEXT: li t1, 0
-; RV64X60-NEXT: addi t2, a7, -1
-; RV64X60-NEXT: add t4, a0, a6
-; RV64X60-NEXT: add t5, a2, a6
-; RV64X60-NEXT: add t3, a4, a6
-; RV64X60-NEXT: zext.w s0, t2
-; RV64X60-NEXT: mul s1, a1, s0
-; RV64X60-NEXT: add t4, t4, s1
-; RV64X60-NEXT: mul s1, a3, s0
-; RV64X60-NEXT: add t5, t5, s1
+; RV64X60-NEXT: addi s1, a7, -1
+; RV64X60-NEXT: zext.w s1, s1
+; RV64X60-NEXT: mul t2, a1, s1
+; RV64X60-NEXT: mul t3, a3, s1
+; RV64X60-NEXT: mul t4, a5, s1
+; RV64X60-NEXT: add s0, a0, a6
+; RV64X60-NEXT: add s1, a2, a6
+; RV64X60-NEXT: add t5, a4, a6
+; RV64X60-NEXT: add s0, s0, t2
; RV64X60-NEXT: csrr t2, vlenb
-; RV64X60-NEXT: mul s1, a5, s0
; RV64X60-NEXT: add t3, t3, s1
-; RV64X60-NEXT: sltu s1, a0, t5
-; RV64X60-NEXT: sltu s0, a2, t4
-; RV64X60-NEXT: and t6, s1, s0
-; RV64X60-NEXT: li t5, 32
-; RV64X60-NEXT: sltu s1, a0, t3
-; RV64X60-NEXT: sltu s0, a4, t4
-; RV64X60-NEXT: and t3, s1, s0
-; RV64X60-NEXT: or s1, a1, a3
-; RV64X60-NEXT: slti s1, s1, 0
-; RV64X60-NEXT: or t4, t6, s1
-; RV64X60-NEXT: or s0, a1, a5
-; RV64X60-NEXT: slti s0, s0, 0
-; RV64X60-NEXT: or s0, t3, s0
+; RV64X60-NEXT: li t6, 32
+; RV64X60-NEXT: add t4, t4, t5
+; RV64X60-NEXT: sltu t3, a0, t3
+; RV64X60-NEXT: sltu s1, a2, s0
+; RV64X60-NEXT: and t3, t3, s1
+; RV64X60-NEXT: or t5, a1, a3
+; RV64X60-NEXT: sltu s1, a0, t4
+; RV64X60-NEXT: sltu s0, a4, s0
+; RV64X60-NEXT: slti t4, t5, 0
+; RV64X60-NEXT: and s0, s0, s1
+; RV64X60-NEXT: or s1, a1, a5
+; RV64X60-NEXT: or t4, t3, t4
; RV64X60-NEXT: slli t3, t2, 1
-; RV64X60-NEXT: maxu s1, t3, t5
+; RV64X60-NEXT: slti s1, s1, 0
+; RV64X60-NEXT: or s0, s0, s1
+; RV64X60-NEXT: maxu s1, t3, t6
; RV64X60-NEXT: or s0, t4, s0
; RV64X60-NEXT: sltu s1, a6, s1
; RV64X60-NEXT: or s0, s0, s1
@@ -339,8 +339,8 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV64X60-NEXT: # in Loop: Header=BB0_4 Depth=1
; RV64X60-NEXT: add t5, t5, a1
; RV64X60-NEXT: add a2, a2, a3
-; RV64X60-NEXT: add a4, a4, a5
; RV64X60-NEXT: addiw t1, t1, 1
+; RV64X60-NEXT: add a4, a4, a5
; RV64X60-NEXT: addi t0, t0, 1
; RV64X60-NEXT: beq t1, a7, .LBB0_11
; RV64X60-NEXT: .LBB0_4: # %for.cond1.preheader.us
@@ -367,10 +367,10 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV64X60-NEXT: vl2r.v v8, (s2)
; RV64X60-NEXT: vl2r.v v10, (s3)
; RV64X60-NEXT: sub s1, s1, t3
-; RV64X60-NEXT: add s3, s3, t3
; RV64X60-NEXT: vaaddu.vv v8, v8, v10
; RV64X60-NEXT: vs2r.v v8, (s4)
; RV64X60-NEXT: add s4, s4, t3
+; RV64X60-NEXT: add s3, s3, t3
; RV64X60-NEXT: add s2, s2, t3
; RV64X60-NEXT: bnez s1, .LBB0_7
; RV64X60-NEXT: # %bb.8: # %middle.block
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
new file mode 100644
index 0000000000000..ceab015e27203
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
@@ -0,0 +1,312 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Zalrsc
+lr.w t0, (t1)
+lr.w.aq t1, (t2)
+lr.w.rl t2, (t3)
+lr.w.aqrl t3, (t4)
+sc.w t6, t5, (t4)
+sc.w.aq t5, t4, (t3)
+sc.w.rl t4, t3, (t2)
+sc.w.aqrl t3, t2, (t1)
+
+lr.d t0, (t1)
+lr.d.aq t1, (t2)
+lr.d.rl t2, (t3)
+lr.d.aqrl t3, (t4)
+sc.d t6, t5, (t4)
+sc.d.aq t5, t4, (t3)
+sc.d.rl t4, t3, (t2)
+sc.d.aqrl t3, t2, (t1)
+
+# Zaamo
+amoswap.w a4, ra, (s0)
+amoadd.w a1, a2, (a3)
+amoxor.w a2, a3, (a4)
+amoand.w a3, a4, (a5)
+amoor.w a4, a5, (a6)
+amomin.w a5, a6, (a7)
+amomax.w s7, s6, (s5)
+amominu.w s6, s5, (s4)
+amomaxu.w s5, s4, (s3)
+
+amoswap.w.aq a4, ra, (s0)
+amoadd.w.aq a1, a2, (a3)
+amoxor.w.aq a2, a3, (a4)
+amoand.w.aq a3, a4, (a5)
+amoor.w.aq a4, a5, (a6)
+amomin.w.aq a5, a6, (a7)
+amomax.w.aq s7, s6, (s5)
+amominu.w.aq s6, s5, (s4)
+amomaxu.w.aq s5, s4, (s3)
+
+amoswap.w.rl a4, ra, (s0)
+amoadd.w.rl a1, a2, (a3)
+amoxor.w.rl a2, a3, (a4)
+amoand.w.rl a3, a4, (a5)
+amoor.w.rl a4, a5, (a6)
+amomin.w.rl a5, a6, (a7)
+amomax.w.rl s7, s6, (s5)
+amominu.w.rl s6, s5, (s4)
+amomaxu.w.rl s5, s4, (s3)
+
+amoswap.w.aqrl a4, ra, (s0)
+amoadd.w.aqrl a1, a2, (a3)
+amoxor.w.aqrl a2, a3, (a4)
+amoand.w.aqrl a3, a4, (a5)
+amoor.w.aqrl a4, a5, (a6)
+amomin.w.aqrl a5, a6, (a7)
+amomax.w.aqrl s7, s6, (s5)
+amominu.w.aqrl s6, s5, (s4)
+amomaxu.w.aqrl s5, s4, (s3)
+
+amoswap.d a4, ra, (s0)
+amoadd.d a1, a2, (a3)
+amoxor.d a2, a3, (a4)
+amoand.d a3, a4, (a5)
+amoor.d a4, a5, (a6)
+amomin.d a5, a6, (a7)
+amomax.d s7, s6, (s5)
+amominu.d s6, s5, (s4)
+amomaxu.d s5, s4, (s3)
+
+amoswap.d.aq a4, ra, (s0)
+amoadd.d.aq a1, a2, (a3)
+amoxor.d.aq a2, a3, (a4)
+amoand.d.aq a3, a4, (a5)
+amoor.d.aq a4, a5, (a6)
+amomin.d.aq a5, a6, (a7)
+amomax.d.aq s7, s6, (s5)
+amominu.d.aq s6, s5, (s4)
+amomaxu.d.aq s5, s4, (s3)
+
+amoswap.d.rl a4, ra, (s0)
+amoadd.d.rl a1, a2, (a3)
+amoxor.d.rl a2, a3, (a4)
+amoand.d.rl a3, a4, (a5)
+amoor.d.rl a4, a5, (a6)
+amomin.d.rl a5, a6, (a7)
+amomax.d.rl s7, s6, (s5)
+amominu.d.rl s6, s5, (s4)
+amomaxu.d.rl s5, s4, (s3)
+
+amoswap.d.aqrl a4, ra, (s0)
+amoadd.d.aqrl a1, a2, (a3)
+amoxor.d.aqrl a2, a3, (a4)
+amoand.d.aqrl a3, a4, (a5)
+amoor.d.aqrl a4, a5, (a6)
+amomin.d.aqrl a5, a6, (a7)
+amomax.d.aqrl s7, s6, (s5)
+amominu.d.aqrl s6, s5, (s4)
+amomaxu.d.aqrl s5, s4, (s3)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W lr.w t0, (t1)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W_AQ lr.w.aq t1, (t2)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W_RL lr.w.rl t2, (t3)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W_AQ_RL lr.w.aqrl t3, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W sc.w t6, t5, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W_AQ sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W_RL sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W_AQ_RL sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D lr.d t0, (t1)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D_AQ lr.d.aq t1, (t2)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D_RL lr.d.rl t2, (t3)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D_AQ_RL lr.d.aqrl t3, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D sc.d t6, t5, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D_AQ sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D_RL sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D_AQ_RL sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W amoswap.w a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W amoadd.w a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W amoxor.w a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W amoand.w a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W amoor.w a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W amomin.w a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W amomax.w s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W amominu.w s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W_AQ amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W_AQ amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W_AQ amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W_AQ amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W_AQ amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W_AQ amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W_AQ amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W_AQ amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W_AQ amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W_RL amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W_RL amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W_RL amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W_RL amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W_RL amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W_RL amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W_RL amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W_RL amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W_AQ_RL amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W_AQ_RL amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W_AQ_RL amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W_AQ_RL amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W_AQ_RL amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W_AQ_RL amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W_AQ_RL amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W_AQ_RL amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W_AQ_RL amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D amoswap.d a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D amoadd.d a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D amoxor.d a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D amoand.d a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D amoor.d a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D amomin.d a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D amomax.d s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D amominu.d s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D_AQ amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D_AQ amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D_AQ amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D_AQ amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D_AQ amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D_AQ amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D_AQ amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D_AQ amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D_AQ amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D_RL amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D_RL amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D_RL amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D_RL amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D_RL amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D_RL amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D_RL amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D_RL amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D_AQ_RL amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D_AQ_RL amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D_AQ_RL amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D_AQ_RL amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D_AQ_RL amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D_AQ_RL amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D_AQ_RL amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D_AQ_RL amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D_AQ_RL amomaxu.d.aqrl s5, s4, (s3)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1]
+# CHECK-NEXT: - - - 44.00 44.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] Instructions:
+# CHECK-NEXT: - - - 0.50 0.50 lr.w t0, (t1)
+# CHECK-NEXT: - - - 0.50 0.50 lr.w.aq t1, (t2)
+# CHECK-NEXT: - - - 0.50 0.50 lr.w.rl t2, (t3)
+# CHECK-NEXT: - - - 0.50 0.50 lr.w.aqrl t3, (t4)
+# CHECK-NEXT: - - - 0.50 0.50 sc.w t6, t5, (t4)
+# CHECK-NEXT: - - - 0.50 0.50 sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: - - - 0.50 0.50 sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: - - - 0.50 0.50 sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - 0.50 0.50 lr.d t0, (t1)
+# CHECK-NEXT: - - - 0.50 0.50 lr.d.aq t1, (t2)
+# CHECK-NEXT: - - - 0.50 0.50 lr.d.rl t2, (t3)
+# CHECK-NEXT: - - - 0.50 0.50 lr.d.aqrl t3, (t4)
+# CHECK-NEXT: - - - 0.50 0.50 sc.d t6, t5, (t4)
+# CHECK-NEXT: - - - 0.50 0.50 sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: - - - 0.50 0.50 sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: - - - 0.50 0.50 sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.w a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.w a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.w a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.w a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.w a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.w a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.w s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.w s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.d a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.d a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.d a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.d a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.d a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.d a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.d s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.d s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: - - - 0.50 0.50 amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - 0.50 0.50 amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - 0.50 0.50 amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - 0.50 0.50 amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - 0.50 0.50 amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - 0.50 0.50 amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - 0.50 0.50 amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - 0.50 0.50 amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - 0.50 0.50 amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
new file mode 100644
index 0000000000000..bd3666ef7bb9f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
@@ -0,0 +1,334 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Floating-Point Load and Store Instructions
+## Half-Precision
+flh ft0, 0(a0)
+fsh ft0, 0(a0)
+
+## Single-Precision
+flw ft0, 0(a0)
+fsw ft0, 0(a0)
+
+## Double-Precision
+fld ft0, 0(a0)
+fsd ft0, 0(a0)
+
+# Floating-Point Computational Instructions
+## Half-Precision
+fadd.h f26, f27, f28
+fsub.h f29, f30, f31
+fmul.h ft0, ft1, ft2
+fdiv.h ft3, ft4, ft5
+fsqrt.h ft6, ft7
+fmin.h fa5, fa6, fa7
+fmax.h fs2, fs3, fs4
+fmadd.h f10, f11, f12, f31
+fmsub.h f14, f15, f16, f17
+fnmsub.h f18, f19, f20, f21
+fnmadd.h f22, f23, f24, f25
+
+## Single-Precision
+fadd.s f26, f27, f28
+fsub.s f29, f30, f31
+fmul.s ft0, ft1, ft2
+fdiv.s ft3, ft4, ft5
+fsqrt.s ft6, ft7
+fmin.s fa5, fa6, fa7
+fmax.s fs2, fs3, fs4
+fmadd.s f10, f11, f12, f31
+fmsub.s f14, f15, f16, f17
+fnmsub.s f18, f19, f20, f21
+fnmadd.s f22, f23, f24, f25
+
+## Double-Precision
+fadd.d f26, f27, f28
+fsub.d f29, f30, f31
+fmul.d ft0, ft1, ft2
+fdiv.d ft3, ft4, ft5
+fsqrt.d ft6, ft7
+fmin.d fa5, fa6, fa7
+fmax.d fs2, fs3, fs4
+fmadd.d f10, f11, f12, f31
+fmsub.d f14, f15, f16, f17
+fnmsub.d f18, f19, f20, f21
+fnmadd.d f22, f23, f24, f25
+
+# Floating-Point Conversion and Move Instructions
+## Half-Precision
+fmv.x.h a2, fs7
+fmv.h.x ft1, a6
+
+fcvt.s.h fa0, ft0
+fcvt.s.h fa0, ft0, rup
+
+fcvt.h.s ft2, fa2
+fcvt.d.h fa0, ft0
+
+fcvt.d.h fa0, ft0, rup
+fcvt.h.d ft2, fa2
+
+## Single-Precision
+fcvt.w.s a0, fs5
+fcvt.wu.s a1, fs6
+fcvt.s.w ft11, a4
+fcvt.s.wu ft0, a5
+
+fcvt.l.s a0, ft0
+fcvt.lu.s a1, ft1
+fcvt.s.l ft2, a2
+fcvt.s.lu ft3, a3
+
+fmv.x.w a2, fs7
+fmv.w.x ft1, a6
+
+fsgnj.s fs1, fa0, fa1
+fsgnjn.s fa1, fa3, fa4
+
+## Double-Precision
+fcvt.wu.d a4, ft11
+fcvt.w.d a4, ft11
+fcvt.d.w ft0, a5
+fcvt.d.wu ft1, a6
+
+fcvt.s.d fs5, fs6
+fcvt.d.s fs7, fs8
+
+fcvt.l.d a0, ft0
+fcvt.lu.d a1, ft1
+fcvt.d.l ft3, a3
+fcvt.d.lu ft4, a4
+
+fmv.x.d a2, ft2
+fmv.d.x ft5, a5
+
+fsgnj.d fs1, fa0, fa1
+fsgnjn.d fa1, fa3, fa4
+
+# Floating-Point Compare Instructions
+## Half-Precision
+feq.h a1, fs8, fs9
+flt.h a2, fs10, fs11
+fle.h a3, ft8, ft9
+
+## Single-Precision
+feq.s a1, fs8, fs9
+flt.s a2, fs10, fs11
+fle.s a3, ft8, ft9
+
+## Double-Precision
+feq.d a1, fs8, fs9
+flt.d a2, fs10, fs11
+fle.d a3, ft8, ft9
+
+# Floating-Point Classify Instruction
+## Half-Precision
+fclass.s a3, ft10
+## Single-Precision
+fclass.s a3, ft10
+## Double-Precision
+fclass.d a3, ft10
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS FLH flh ft0, 0(a0)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS FSH fsh ft0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS FLW flw ft0, 0(a0)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS FSW fsw ft0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS FLD fld ft0, 0(a0)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS FSD fsd ft0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FADD_H fadd.h fs10, fs11, ft8
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSUB_H fsub.h ft9, ft10, ft11
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMUL_H fmul.h ft0, ft1, ft2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_FP[12] FDIV_H fdiv.h ft3, ft4, ft5
+# CHECK-NEXT: 1 12 12.00 12 SMX60_FP[12] FSQRT_H fsqrt.h ft6, ft7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMIN_H fmin.h fa5, fa6, fa7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMAX_H fmax.h fs2, fs3, fs4
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMADD_H fmadd.h fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMSUB_H fmsub.h fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMSUB_H fnmsub.h fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMADD_H fnmadd.h fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FADD_S fadd.s fs10, fs11, ft8
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSUB_S fsub.s ft9, ft10, ft11
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMUL_S fmul.s ft0, ft1, ft2
+# CHECK-NEXT: 1 15 15.00 15 SMX60_FP[15] FDIV_S fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: 1 15 15.00 15 SMX60_FP[15] FSQRT_S fsqrt.s ft6, ft7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMIN_S fmin.s fa5, fa6, fa7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMAX_S fmax.s fs2, fs3, fs4
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMADD_S fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMSUB_S fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMSUB_S fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMADD_S fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FADD_D fadd.d fs10, fs11, ft8
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FSUB_D fsub.d ft9, ft10, ft11
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMUL_D fmul.d ft0, ft1, ft2
+# CHECK-NEXT: 1 22 22.00 22 SMX60_FP[22] FDIV_D fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: 1 22 22.00 22 SMX60_FP[22] FSQRT_D fsqrt.d ft6, ft7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMIN_D fmin.d fa5, fa6, fa7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMAX_D fmax.d fs2, fs3, fs4
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FMADD_D fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FMSUB_D fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FNMSUB_D fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FNMADD_D fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FMV_X_H fmv.x.h a2, fs7
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FMV_H_X fmv.h.x ft1, a6
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_S_H fcvt.s.h fa0, ft0
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_S_H fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_H_S fcvt.h.s ft2, fa2
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_D_H fcvt.d.h fa0, ft0
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_D_H fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_H_D fcvt.h.d ft2, fa2
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_W_S fcvt.w.s a0, fs5
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_WU_S fcvt.wu.s a1, fs6
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_S_W fcvt.s.w ft11, a4
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_S_WU fcvt.s.wu ft0, a5
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_L_S fcvt.l.s a0, ft0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_LU_S fcvt.lu.s a1, ft1
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_S_L fcvt.s.l ft2, a2
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_S_LU fcvt.s.lu ft3, a3
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FMV_X_W fmv.x.w a2, fs7
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FMV_W_X fmv.w.x ft1, a6
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSGNJ_S fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSGNJN_S fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_WU_D fcvt.wu.d a4, ft11
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_W_D fcvt.w.d a4, ft11
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_D_W fcvt.d.w ft0, a5
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_D_WU fcvt.d.wu ft1, a6
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_S_D fcvt.s.d fs5, fs6
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_D_S fcvt.d.s fs7, fs8
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_L_D fcvt.l.d a0, ft0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_LU_D fcvt.lu.d a1, ft1
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_D_L fcvt.d.l ft3, a3
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_D_LU fcvt.d.lu ft4, a4
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FMV_X_D fmv.x.d a2, ft2
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FMV_D_X fmv.d.x ft5, a5
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FSGNJ_D fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FSGNJN_D fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FEQ_H feq.h a1, fs8, fs9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLT_H flt.h a2, fs10, fs11
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLE_H fle.h a3, ft8, ft9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FEQ_S feq.s a1, fs8, fs9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLT_S flt.s a2, fs10, fs11
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLE_S fle.s a3, ft8, ft9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FEQ_D feq.d a1, fs8, fs9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLT_D flt.d a2, fs10, fs11
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLE_D fle.d a3, ft8, ft9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FCLASS_S fclass.s a3, ft10
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FCLASS_S fclass.s a3, ft10
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FCLASS_D fclass.d a3, ft10
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1]
+# CHECK-NEXT: 149.00 11.00 11.00 3.00 3.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] Instructions:
+# CHECK-NEXT: - - - 0.50 0.50 flh ft0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 fsh ft0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 flw ft0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 fsw ft0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 fld ft0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 fsd ft0, 0(a0)
+# CHECK-NEXT: 1.00 - - - - fadd.h fs10, fs11, ft8
+# CHECK-NEXT: 1.00 - - - - fsub.h ft9, ft10, ft11
+# CHECK-NEXT: 1.00 - - - - fmul.h ft0, ft1, ft2
+# CHECK-NEXT: 12.00 - - - - fdiv.h ft3, ft4, ft5
+# CHECK-NEXT: 12.00 - - - - fsqrt.h ft6, ft7
+# CHECK-NEXT: 1.00 - - - - fmin.h fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - fmax.h fs2, fs3, fs4
+# CHECK-NEXT: 1.00 - - - - fmadd.h fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1.00 - - - - fmsub.h fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - fnmsub.h fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1.00 - - - - fnmadd.h fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - fadd.s fs10, fs11, ft8
+# CHECK-NEXT: 1.00 - - - - fsub.s ft9, ft10, ft11
+# CHECK-NEXT: 1.00 - - - - fmul.s ft0, ft1, ft2
+# CHECK-NEXT: 15.00 - - - - fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: 15.00 - - - - fsqrt.s ft6, ft7
+# CHECK-NEXT: 1.00 - - - - fmin.s fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - fmax.s fs2, fs3, fs4
+# CHECK-NEXT: 1.00 - - - - fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1.00 - - - - fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1.00 - - - - fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - fadd.d fs10, fs11, ft8
+# CHECK-NEXT: 1.00 - - - - fsub.d ft9, ft10, ft11
+# CHECK-NEXT: 1.00 - - - - fmul.d ft0, ft1, ft2
+# CHECK-NEXT: 22.00 - - - - fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: 22.00 - - - - fsqrt.d ft6, ft7
+# CHECK-NEXT: 1.00 - - - - fmin.d fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - fmax.d fs2, fs3, fs4
+# CHECK-NEXT: 1.00 - - - - fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1.00 - - - - fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1.00 - - - - fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: - 0.50 0.50 - - fmv.x.h a2, fs7
+# CHECK-NEXT: - 0.50 0.50 - - fmv.h.x ft1, a6
+# CHECK-NEXT: 1.00 - - - - fcvt.s.h fa0, ft0
+# CHECK-NEXT: 1.00 - - - - fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: 1.00 - - - - fcvt.h.s ft2, fa2
+# CHECK-NEXT: 1.00 - - - - fcvt.d.h fa0, ft0
+# CHECK-NEXT: 1.00 - - - - fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: 1.00 - - - - fcvt.h.d ft2, fa2
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.w.s a0, fs5
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.wu.s a1, fs6
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.s.w ft11, a4
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.s.wu ft0, a5
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.l.s a0, ft0
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.lu.s a1, ft1
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.s.l ft2, a2
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.s.lu ft3, a3
+# CHECK-NEXT: - 0.50 0.50 - - fmv.x.w a2, fs7
+# CHECK-NEXT: - 0.50 0.50 - - fmv.w.x ft1, a6
+# CHECK-NEXT: 1.00 - - - - fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: 1.00 - - - - fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.wu.d a4, ft11
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.w.d a4, ft11
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.d.w ft0, a5
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.d.wu ft1, a6
+# CHECK-NEXT: 1.00 - - - - fcvt.s.d fs5, fs6
+# CHECK-NEXT: 1.00 - - - - fcvt.d.s fs7, fs8
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.l.d a0, ft0
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.lu.d a1, ft1
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.d.l ft3, a3
+# CHECK-NEXT: - 0.50 0.50 - - fcvt.d.lu ft4, a4
+# CHECK-NEXT: - 0.50 0.50 - - fmv.x.d a2, ft2
+# CHECK-NEXT: - 0.50 0.50 - - fmv.d.x ft5, a5
+# CHECK-NEXT: 1.00 - - - - fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: 1.00 - - - - fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: 1.00 - - - - feq.h a1, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - flt.h a2, fs10, fs11
+# CHECK-NEXT: 1.00 - - - - fle.h a3, ft8, ft9
+# CHECK-NEXT: 1.00 - - - - feq.s a1, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - flt.s a2, fs10, fs11
+# CHECK-NEXT: 1.00 - - - - fle.s a3, ft8, ft9
+# CHECK-NEXT: 1.00 - - - - feq.d a1, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - flt.d a2, fs10, fs11
+# CHECK-NEXT: 1.00 - - - - fle.d a3, ft8, ft9
+# CHECK-NEXT: 1.00 - - - - fclass.s a3, ft10
+# CHECK-NEXT: 1.00 - - - - fclass.s a3, ft10
+# CHECK-NEXT: 1.00 - - - - fclass.d a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
new file mode 100644
index 0000000000000..8b43874499f2b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
@@ -0,0 +1,431 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Integer Register-Immediate Instructions
+addi a0, a0, 1
+addiw a0, a0, 1
+slti a0, a0, 1
+sltiu a0, a0, 1
+
+andi a0, a0, 1
+ori a0, a0, 1
+xori a0, a0, 1
+
+slli a0, a0, 1
+srli a0, a0, 1
+srai a0, a0, 1
+slliw a0, a0, 1
+srliw a0, a0, 1
+sraiw a0, a0, 1
+
+lui a0, 1
+auipc a1, 1
+
+# Integer Register-Register Operations
+add a0, a0, a1
+addw a0, a0, a0
+slt a0, a0, a0
+sltu a0, a0, a0
+
+and a0, a0, a0
+or a0, a0, a0
+xor a0, a0, a0
+
+sll a0, a0, a0
+srl a0, a0, a0
+sra a0, a0, a0
+sllw a0, a0, a0
+srlw a0, a0, a0
+sraw a0, a0, a0
+
+sub a0, a0, a0
+subw a0, a0, a0
+
+# Control Transfer Instructions
+
+## Unconditional Jumps
+jal a0, 1f
+1:
+jalr a0
+beq a0, a0, 1f
+1:
+bne a0, a0, 1f
+1:
+blt a0, a0, 1f
+1:
+bltu a0, a0, 1f
+1:
+bge a0, a0, 1f
+1:
+bgeu a0, a0, 1f
+1:
+add a0, a0, a0
+
+# Load and Store Instructions
+lb t0, 0(a0)
+lbu t0, 0(a0)
+lh t0, 0(a0)
+lhu t0, 0(a0)
+lw t0, 0(a0)
+lwu t0, 0(a0)
+ld t0, 0(a0)
+
+sb t0, 0(a0)
+sh t0, 0(a0)
+sw t0, 0(a0)
+sd t0, 0(a0)
+
+# Multiply/Division
+mul a0, a0, a0
+mulh a0, a0, a0
+mulhu a0, a0, a0
+mulhsu a0, a0, a0
+mulw a0, a0, a0
+div a0, a1, a2
+divu a0, a1, a2
+rem a0, a1, a2
+remu a0, a1, a2
+divw a0, a1, a2
+divuw a0, a1, a2
+remw a0, a1, a2
+remuw a0, a1, a2
+
+# Zicsr
+csrrw t0, 0xfff, t1
+csrrs s3, 0x001, s5
+csrrc sp, 0x000, ra
+csrrwi a5, 0x000, 0
+csrrsi t2, 0xfff, 31
+csrrci t1, 0x140, 5
+
+# Zicond
+czero.eqz a0, a1, a2
+czero.nez a0, a1, a2
+
+# Zicond
+czero.eqz a0, a1, a2
+czero.nez a0, a1, a2
+
+# Zba
+add.uw a0, a0, a0
+slli.uw a0, a0, 1
+sh1add.uw a0, a0, a0
+sh2add.uw a0, a0, a0
+sh3add.uw a0, a0, a0
+sh1add a0, a0, a0
+sh2add a0, a0, a0
+sh3add a0, a0, a0
+
+# Zbb
+andn a0, a0, a0
+orn a0, a0, a0
+xnor a0, a0, a0
+
+clz a0, a0
+clzw a0, a0
+ctz a0, a0
+ctzw a0, a0
+
+cpop a0, a0
+cpopw a0, a0
+
+min a0, a0, a0
+minu a0, a0, a0
+max a0, a0, a0
+maxu a0, a0, a0
+
+sext.b a0, a0
+sext.h a0, a0
+zext.h a0, a0
+
+rol a0, a0, a0
+rolw a0, a0, a0
+ror a0, a0, a0
+rorw a0, a0, a0
+rori a0, a0, 1
+roriw a0, a0, 1
+
+orc.b a0, a0
+
+rev8 a0, a0
+
+# Zbc
+clmul a0, a0, a0
+clmulr a0, a0, a0
+clmulh a0, a0, a0
+
+# Zbs
+bclr a0, a1, a2
+bclri a0, a1, 1
+bext a0, a1, a2
+bexti a0, a1, 1
+binv a0, a1, a2
+binvi a0, a1, 1
+bset a0, a1, a2
+bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDI addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDIW addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTI slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTIU seqz a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ANDI andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORI ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU XORI xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SLLI slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SRLI srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SRAI srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLIW slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRLIW srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRAIW sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_LUI lui a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU AUIPC auipc a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADD add a0, a0, a1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDW addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLT slt a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTU sltu a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_AND and a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_OR or a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_XOR xor a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLL sll a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRL srl a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRA sra a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLW sllw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRLW srlw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRAW sraw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SUB sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SUBW subw a0, a0, a0
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA JAL jal a0, .Ltmp0
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA C_JALR jalr a0
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BEQ beq a0, a0, .Ltmp1
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BNE bne a0, a0, .Ltmp2
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BLT blt a0, a0, .Ltmp3
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BLTU bltu a0, a0, .Ltmp4
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGE bge a0, a0, .Ltmp5
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGEU bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADD add a0, a0, a0
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LB lb t0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LBU lbu t0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LH lh t0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LHU lhu t0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LW lw t0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LWU lwu t0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LD ld t0, 0(a0)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SB sb t0, 0(a0)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SH sh t0, 0(a0)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SW sw t0, 0(a0)
+# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SD sd t0, 0(a0)
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MUL mul a0, a0, a0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULH mulh a0, a0, a0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHU mulhu a0, a0, a0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHSU mulhsu a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 SMX60_IEU MULW mulw a0, a0, a0
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIV div a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIVU divu a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REM rem a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REMU remu a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVW divw a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVUW divuw a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMW remw a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMUW remuw a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRW csrrw t0, 4095, t1
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRS csrrs s3, fflags, s5
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRC csrrc sp, 0, ra
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRWI csrrwi a5, 0, 0
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRSI csrrsi t2, 4095, 31
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRCI csrrci t1, sscratch, 5
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_EQZ czero.eqz a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_NEZ czero.nez a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_EQZ czero.eqz a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_NEZ czero.nez a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ADD_UW add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLI_UW slli.uw a0, a0, 1
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH1ADD_UW sh1add.uw a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH2ADD_UW sh2add.uw a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH3ADD_UW sh3add.uw a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH1ADD sh1add a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH2ADD sh2add a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH3ADD sh3add a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ANDN andn a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORN orn a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU XNOR xnor a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CLZ clz a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CLZW clzw a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CTZ ctz a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CTZW ctzw a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CPOP cpop a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CPOPW cpopw a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MIN min a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MINU minu a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MAX max a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MAXU maxu a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SEXT_B sext.b a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SEXT_H sext.h a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ZEXT_H_RV64 zext.h a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROL rol a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROLW rolw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROR ror a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORW rorw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORI rori a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORIW roriw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORC_B orc.b a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU REV8_RV64 rev8 a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMUL clmul a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMULR clmulr a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMULH clmulh a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BCLR bclr a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BCLRI bclri a0, a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BEXT bext a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BEXTI bexti a0, a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BINV binv a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BINVI binvi a0, a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BSET bset a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BSETI bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1]
+# CHECK-NEXT: - 180.50 44.50 5.50 5.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - addi a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - addiw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - slti a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - seqz a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - andi a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - ori a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - xori a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - slli a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - srli a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - srai a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - slliw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - srliw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - sraiw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - lui a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - auipc a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - add a0, a0, a1
+# CHECK-NEXT: - 0.50 0.50 - - addw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - slt a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sltu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - and a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - or a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - xor a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sll a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - srl a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sra a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sllw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - srlw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sraw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sub a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - subw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - jal a0, .Ltmp0
+# CHECK-NEXT: - 1.00 - - - jalr a0
+# CHECK-NEXT: - 1.00 - - - beq a0, a0, .Ltmp1
+# CHECK-NEXT: - 1.00 - - - bne a0, a0, .Ltmp2
+# CHECK-NEXT: - 1.00 - - - blt a0, a0, .Ltmp3
+# CHECK-NEXT: - 1.00 - - - bltu a0, a0, .Ltmp4
+# CHECK-NEXT: - 1.00 - - - bge a0, a0, .Ltmp5
+# CHECK-NEXT: - 1.00 - - - bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: - 0.50 0.50 - - add a0, a0, a0
+# CHECK-NEXT: - - - 0.50 0.50 lb t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 lbu t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 lh t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 lhu t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 lw t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 lwu t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 ld t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 sb t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 sh t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 sw t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 sd t0, 0(a0)
+# CHECK-NEXT: - 0.50 0.50 - - mul a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - mulh a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - mulhu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - mulhsu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - mulw a0, a0, a0
+# CHECK-NEXT: - 20.00 - - - div a0, a1, a2
+# CHECK-NEXT: - 20.00 - - - divu a0, a1, a2
+# CHECK-NEXT: - 20.00 - - - rem a0, a1, a2
+# CHECK-NEXT: - 20.00 - - - remu a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - divw a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - divuw a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - remw a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - remuw a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - csrrw t0, 4095, t1
+# CHECK-NEXT: - 0.50 0.50 - - csrrs s3, fflags, s5
+# CHECK-NEXT: - 0.50 0.50 - - csrrc sp, 0, ra
+# CHECK-NEXT: - 0.50 0.50 - - csrrwi a5, 0, 0
+# CHECK-NEXT: - 0.50 0.50 - - csrrsi t2, 4095, 31
+# CHECK-NEXT: - 0.50 0.50 - - csrrci t1, sscratch, 5
+# CHECK-NEXT: - 0.50 0.50 - - czero.eqz a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - czero.nez a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - czero.eqz a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - czero.nez a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - slli.uw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sh2add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sh3add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sh1add a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sh2add a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sh3add a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - andn a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - orn a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - xnor a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - clz a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - clzw a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - ctz a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - ctzw a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - cpop a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - cpopw a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - min a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - minu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - max a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - maxu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sext.b a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - sext.h a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - zext.h a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - rol a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - rolw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - ror a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - rorw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - rori a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - roriw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - orc.b a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - rev8 a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - clmul a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - clmulr a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - clmulh a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - bclr a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - bclri a0, a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - bext a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - bexti a0, a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - binv a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - binvi a0, a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - bset a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - bseti a0, a1, 1
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