[llvm] 91ad90b - [MISched][NFC] Precommit test for #137988 (#138243)

[via llvm-commits]

Author: Cullen Rhodes
Date: 2025-05-06T08:48:37+01:00
New Revision: 91ad90bc4cbd5dd8ba3e5d2c138d576e2ae748ab

URL: https://github.com/llvm/llvm-project/commit/91ad90bc4cbd5dd8ba3e5d2c138d576e2ae748ab
DIFF: https://github.com/llvm/llvm-project/commit/91ad90bc4cbd5dd8ba3e5d2c138d576e2ae748ab.diff

LOG: [MISched][NFC] Precommit test for #137988 (#138243)

Added: 
    llvm/test/CodeGen/AArch64/misched-cutoff.mir

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/misched-cutoff.mir b/llvm/test/CodeGen/AArch64/misched-cutoff.mir
new file mode 100644
index 0000000000000..a81fe1102ac9f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-cutoff.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes=machine-scheduler -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes=machine-scheduler -misched-cutoff=1 -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-CUTOFF
+
+# REQUIRES: asserts
+
+# CHECK-CUTOFF-COUNT-2: Scheduling SU
+
+# NOTE: copied from machine-scheduler.mir
+
+--- |
+  define i64 @load_imp-def(ptr nocapture %P, i32 %v) {
+  entry:
+    %0 = bitcast ptr %P to ptr
+    %1 = load i32, ptr %0
+    %conv = zext i32 %1 to i64
+    %arrayidx19 = getelementptr inbounds i64, ptr %P, i64 1
+    %arrayidx1 = bitcast ptr %arrayidx19 to ptr
+    store i32 %v, ptr %arrayidx1
+    %2 = load i64, ptr %arrayidx19
+    %and = and i64 %2, 4294967295
+    %add = add nuw nsw i64 %and, %conv
+    ret i64 %add
+  }
+...
+---
+name: load_imp-def
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $w1, $x0
+    ; CHECK-LABEL: name: load_imp-def
+    ; CHECK: liveins: $w1, $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $w8 = LDRWui $x0, 1, implicit-def $x8 :: (load (s32) from %ir.0)
+    ; CHECK-NEXT: $w9 = LDRWui $x0, 0, implicit-def $x9 :: (load (s32) from %ir.arrayidx19, align 8)
+    ; CHECK-NEXT: STRWui $w1, $x0, 2 :: (store (s32) into %ir.arrayidx1)
+    ; CHECK-NEXT: $x0 = ADDXrr killed $x9, killed $x8
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    ;
+    ; CHECK-CUTOFF-LABEL: name: load_imp-def
+    ; CHECK-CUTOFF: liveins: $w1, $x0
+    ; CHECK-CUTOFF-NEXT: {{  $}}
+    ; CHECK-CUTOFF-NEXT: $w8 = LDRWui $x0, 1, implicit-def $x8 :: (load (s32) from %ir.0)
+    ; CHECK-CUTOFF-NEXT: STRWui $w1, $x0, 2 :: (store (s32) into %ir.arrayidx1)
+    ; CHECK-CUTOFF-NEXT: $w9 = LDRWui $x0, 0, implicit-def $x9 :: (load (s32) from %ir.arrayidx19, align 8)
+    ; CHECK-CUTOFF-NEXT: $x0 = ADDXrr killed $x9, killed $x8
+    ; CHECK-CUTOFF-NEXT: RET_ReallyLR implicit $x0
+    $w8 = LDRWui $x0, 1, implicit-def $x8  :: (load (s32) from %ir.0)
+    STRWui killed $w1, $x0, 2 :: (store (s32) into %ir.arrayidx1)
+    $w9 = LDRWui killed $x0, 0, implicit-def $x9  :: (load (s32) from %ir.arrayidx19, align 8)
+    $x0 = ADDXrr killed $x9, killed $x8
+    RET_ReallyLR implicit $x0
+...
+