[llvm] f54f4cf - [RISCV] Add compress patterns for Xqcisync instructions (#138629)

[via llvm-commits]

Author: Sudharsan Veeravalli
Date: 2025-05-06T13:05:56+05:30
New Revision: f54f4cf262bd286c6f14f4faae035a4df9db32e8

URL: https://github.com/llvm/llvm-project/commit/f54f4cf262bd286c6f14f4faae035a4df9db32e8
DIFF: https://github.com/llvm/llvm-project/commit/f54f4cf262bd286c6f14f4faae035a4df9db32e8.diff

LOG: [RISCV] Add compress patterns for Xqcisync instructions (#138629)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    llvm/test/MC/RISCV/xqcisync-valid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 58b6c08ad0d05..5ff140ce2e4b4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -75,6 +75,15 @@ def uimm5slist : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
   let EncoderMethod = "getImmOpValueSlist";
   let DecoderMethod = "decodeUImmSlistOperand";
   let OperandType = "OPERAND_UIMM5_SLIST";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return ((Imm == 0)  || (Imm == 1)  ||
+            (Imm == 2)  || (Imm == 4)  ||
+            (Imm == 8)  || (Imm == 16) ||
+            (Imm == 15) || (Imm == 31));
+  }];
 }
 
 def uimm10 : RISCVUImmLeafOp<10>;
@@ -1341,6 +1350,13 @@ def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
+let Predicates = [HasVendorXqcisync, IsRV32] in {
+def : CompressPat<(QC_SYNC uimm5slist:$imm5), (QC_C_SYNC uimm5slist:$imm5)>;
+def : CompressPat<(QC_SYNCR uimm5slist:$imm5), (QC_C_SYNCR uimm5slist:$imm5)>;
+def : CompressPat<(QC_SYNCWL uimm5slist:$imm5), (QC_C_SYNCWL uimm5slist:$imm5)>;
+def : CompressPat<(QC_SYNCWF uimm5slist:$imm5), (QC_C_SYNCWF uimm5slist:$imm5)>;
+} // Predicates = [HasVendorXqcisync, IsRV32]
+
 let isCompressOnly = true, Predicates = [HasVendorXqcilo, HasStdExtZcb, IsRV32] in {
 def : CompressPat<(QC_E_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm),
                   (C_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm)>;

diff  --git a/llvm/test/MC/RISCV/xqcisync-valid.s b/llvm/test/MC/RISCV/xqcisync-valid.s
index 4f0063a6a488c..84ea74b74564f 100644
--- a/llvm/test/MC/RISCV/xqcisync-valid.s
+++ b/llvm/test/MC/RISCV/xqcisync-valid.s
@@ -1,11 +1,11 @@
 # Xqcisync - Qualcomm uC Sync Delay Extension
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcisync -M no-aliases --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcisync --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
@@ -14,34 +14,60 @@
 # CHECK-ENC: encoding: [0x2a,0x00]
 qc.c.delay 10
 
-# CHECK-INST: qc.sync      8
-# CHECK-ENC: encoding: [0x13,0x30,0x80,0x10]
-qc.sync 8
+# CHECK-INST: qc.sync      9
+# CHECK-ENC: encoding: [0x13,0x30,0x90,0x10]
+qc.sync 9
 
 # CHECK-INST: qc.syncr     23
 # CHECK-ENC: encoding: [0x13,0x30,0x70,0x21]
 qc.syncr 23
 
-# CHECK-INST: qc.syncwf    31
-# CHECK-ENC: encoding: [0x13,0x30,0xf0,0x41]
-qc.syncwf 31
+# CHECK-INST: qc.syncwf    30
+# CHECK-ENC: encoding: [0x13,0x30,0xe0,0x41]
+qc.syncwf 30
 
-# CHECK-INST: qc.syncwl    1
-# CHECK-ENC: encoding: [0x13,0x30,0x10,0x80]
-qc.syncwl 1
+# CHECK-INST: qc.syncwl    6
+# CHECK-ENC: encoding: [0x13,0x30,0x60,0x80]
+qc.syncwl 6
 
-# CHECK-INST: qc.c.sync      0
+# CHECK-NOALIAS: qc.c.sync      0
+# CHECK-ALIAS: qc.sync 0
 # CHECK-ENC: encoding: [0x01,0x80]
 qc.c.sync 0
 
-# CHECK-INST: qc.c.syncr     15
+# CHECK-NOALIAS: qc.c.syncr     15
+# CHECK-ALIAS: qc.syncr 15
 # CHECK-ENC: encoding: [0x01,0x87]
 qc.c.syncr 15
 
-# CHECK-INST: qc.c.syncwf    31
+# CHECK-NOALIAS: qc.c.syncwf    31
+# CHECK-ALIAS: qc.syncwf 31
 # CHECK-ENC: encoding: [0x81,0x93]
 qc.c.syncwf 31
 
-# CHECK-INST: qc.c.syncwl    4
+# CHECK-NOALIAS: qc.c.syncwl    4
+# CHECK-ALIAS: qc.syncwl 4
 # CHECK-ENC: encoding: [0x81,0x95]
 qc.c.syncwl 4
+
+# Check that compressed patterns work
+
+# CHECK-NOALIAS: qc.c.sync      8
+# CHECK-ALIAS: qc.sync 8
+# CHECK-ENC: encoding: [0x01,0x82]
+qc.sync 8
+
+# CHECK-NOALIAS: qc.c.syncr     31
+# CHECK-ALIAS: qc.syncr 31
+# CHECK-ENC: encoding: [0x81,0x87]
+qc.syncr 31
+
+# CHECK-NOALIAS: qc.c.syncwf    0
+# CHECK-ALIAS: qc.syncwf 0
+# CHECK-ENC: encoding: [0x01,0x90]
+qc.syncwf 0
+
+# CHECK-NOALIAS: qc.c.syncwl    16
+# CHECK-ALIAS: qc.syncwl 16
+# CHECK-ENC: encoding: [0x81,0x96]
+qc.syncwl 16