[llvm] [Hexagon] Use TargetInstrInfo::RegSubRegPair (PR #138637)
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Mon May 5 23:39:17 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-hexagon
Author: Sudharsan Veeravalli (svs-quic)
<details>
<summary>Changes</summary>
Use the RegSubRegPair struct defined in TargetInstrInfo instead of the custom definitions in HexagonGenPredicates and HexagonConstantPropogation.
This patch addresses the FIXME's that were there in these passes.
---
Patch is 44.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/138637.diff
3 Files Affected:
- (modified) llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp (+152-140)
- (modified) llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp (+57-70)
- (modified) llvm/lib/Target/Hexagon/HexagonInstrInfo.h (+7)
``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index a0a67bed45e74..740479174c814 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -77,27 +77,7 @@ namespace {
static uint32_t deduce(const Constant *C);
};
- // A representation of a register as it can appear in a MachineOperand,
- // i.e. a pair register:subregister.
-
- // FIXME: Use TargetInstrInfo::RegSubRegPair. Also duplicated in
- // HexagonGenPredicate
- struct RegisterSubReg {
- Register Reg;
- unsigned SubReg;
-
- explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
- explicit RegisterSubReg(const MachineOperand &MO)
- : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
-
- void print(const TargetRegisterInfo *TRI = nullptr) const {
- dbgs() << printReg(Reg, TRI, SubReg);
- }
-
- bool operator== (const RegisterSubReg &R) const {
- return (Reg == R.Reg) && (SubReg == R.SubReg);
- }
- };
+ using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
// Lattice cell, based on that was described in the W-Z paper on constant
// propagation.
@@ -312,7 +292,7 @@ namespace {
using CellMap = MachineConstPropagator::CellMap;
virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs) = 0;
- virtual bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
+ virtual bool evaluate(const RegSubRegPair &R, const LatticeCell &SrcC,
LatticeCell &Result) = 0;
virtual bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
SetVector<const MachineBasicBlock*> &Targets,
@@ -355,17 +335,19 @@ namespace {
// Helper functions.
- bool getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC);
+ bool getCell(const RegSubRegPair &R, const CellMap &Inputs,
+ LatticeCell &RC);
bool constToInt(const Constant *C, APInt &Val) const;
const ConstantInt *intToConst(const APInt &Val) const;
// Compares.
- bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, bool &Result);
- bool evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, bool &Result);
- bool evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2,
- const CellMap &Inputs, bool &Result);
+ bool evaluateCMPrr(uint32_t Cmp, const RegSubRegPair &R1,
+ const RegSubRegPair &R2, const CellMap &Inputs,
+ bool &Result);
+ bool evaluateCMPri(uint32_t Cmp, const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, bool &Result);
+ bool evaluateCMPrp(uint32_t Cmp, const RegSubRegPair &R1, uint64_t Props2,
+ const CellMap &Inputs, bool &Result);
bool evaluateCMPii(uint32_t Cmp, const APInt &A1, const APInt &A2,
bool &Result);
bool evaluateCMPpi(uint32_t Cmp, uint32_t Props, const APInt &A2,
@@ -373,53 +355,53 @@ namespace {
bool evaluateCMPpp(uint32_t Cmp, uint32_t Props1, uint32_t Props2,
bool &Result);
- bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs,
- LatticeCell &Result);
+ bool evaluateCOPY(const RegSubRegPair &R1, const CellMap &Inputs,
+ LatticeCell &Result);
// Logical operations.
- bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, LatticeCell &Result);
- bool evaluateANDri(const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateANDrr(const RegSubRegPair &R1, const RegSubRegPair &R2,
+ const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateANDri(const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateANDii(const APInt &A1, const APInt &A2, APInt &Result);
- bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, LatticeCell &Result);
- bool evaluateORri(const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateORrr(const RegSubRegPair &R1, const RegSubRegPair &R2,
+ const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateORri(const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateORii(const APInt &A1, const APInt &A2, APInt &Result);
- bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, LatticeCell &Result);
- bool evaluateXORri(const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateXORrr(const RegSubRegPair &R1, const RegSubRegPair &R2,
+ const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateXORri(const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateXORii(const APInt &A1, const APInt &A2, APInt &Result);
// Extensions.
- bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateZEXTr(const RegSubRegPair &R1, unsigned Width, unsigned Bits,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateZEXTi(const APInt &A1, unsigned Width, unsigned Bits,
APInt &Result);
- bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateSEXTr(const RegSubRegPair &R1, unsigned Width, unsigned Bits,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateSEXTi(const APInt &A1, unsigned Width, unsigned Bits,
APInt &Result);
// Leading/trailing bits.
- bool evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateCLBr(const RegSubRegPair &R1, bool Zeros, bool Ones,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateCLBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
- bool evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateCTBr(const RegSubRegPair &R1, bool Zeros, bool Ones,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateCTBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
// Bitfield extract.
- bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
- unsigned Offset, bool Signed, const CellMap &Inputs,
- LatticeCell &Result);
+ bool evaluateEXTRACTr(const RegSubRegPair &R1, unsigned Width,
+ unsigned Bits, unsigned Offset, bool Signed,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateEXTRACTi(const APInt &A1, unsigned Bits, unsigned Offset,
bool Signed, APInt &Result);
// Vector operations.
- bool evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateSplatr(const RegSubRegPair &R1, unsigned Bits, unsigned Count,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateSplati(const APInt &A1, unsigned Bits, unsigned Count,
APInt &Result);
};
@@ -630,7 +612,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
const MachineOperand &MD = PN.getOperand(0);
- RegisterSubReg DefR(MD);
+ RegSubRegPair DefR(getRegSubRegPair(MD));
assert(DefR.Reg.isVirtual());
bool Changed = false;
@@ -657,7 +639,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
continue;
}
const MachineOperand &SO = PN.getOperand(i);
- RegisterSubReg UseR(SO);
+ RegSubRegPair UseR(getRegSubRegPair(SO));
// If the input is not a virtual register, we don't really know what
// value it holds.
if (!UseR.Reg.isVirtual())
@@ -700,7 +682,7 @@ void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- RegisterSubReg DefR(MO);
+ RegSubRegPair DefR(getRegSubRegPair(MO));
// Only track virtual registers.
if (!DefR.Reg.isVirtual())
continue;
@@ -1075,8 +1057,8 @@ bool MachineConstPropagator::run(MachineFunction &MF) {
// --------------------------------------------------------------------
// Machine const evaluator.
-bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
- LatticeCell &RC) {
+bool MachineConstEvaluator::getCell(const RegSubRegPair &R,
+ const CellMap &Inputs, LatticeCell &RC) {
if (!R.Reg.isVirtual())
return false;
const LatticeCell &L = Inputs.get(R.Reg);
@@ -1101,8 +1083,9 @@ const ConstantInt *MachineConstEvaluator::intToConst(const APInt &Val) const {
return ConstantInt::get(CX, Val);
}
-bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) {
+bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs, bool &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
LatticeCell LS1, LS2;
if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
@@ -1140,8 +1123,9 @@ bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1
return IsTrue || IsFalse;
}
-bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, bool &Result) {
+bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegSubRegPair &R1,
+ const APInt &A2,
+ const CellMap &Inputs, bool &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS;
if (!getCell(R1, Inputs, LS))
@@ -1167,8 +1151,9 @@ bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1
return IsTrue || IsFalse;
}
-bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1,
- uint64_t Props2, const CellMap &Inputs, bool &Result) {
+bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegSubRegPair &R1,
+ uint64_t Props2,
+ const CellMap &Inputs, bool &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS;
if (!getCell(R1, Inputs, LS))
@@ -1360,13 +1345,16 @@ bool MachineConstEvaluator::evaluateCMPpp(uint32_t Cmp, uint32_t Props1,
return false;
}
-bool MachineConstEvaluator::evaluateCOPY(const RegisterSubReg &R1,
- const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateCOPY(const RegSubRegPair &R1,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
return getCell(R1, Inputs, Result);
}
-bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateANDrr(const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
const LatticeCell &L1 = Inputs.get(R2.Reg);
const LatticeCell &L2 = Inputs.get(R2.Reg);
@@ -1396,8 +1384,10 @@ bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1,
return !Result.isBottom();
}
-bool MachineConstEvaluator::evaluateANDri(const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateANDri(const RegSubRegPair &R1,
+ const APInt &A2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
if (A2 == -1)
return getCell(R1, Inputs, Result);
@@ -1432,8 +1422,10 @@ bool MachineConstEvaluator::evaluateANDii(const APInt &A1,
return true;
}
-bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateORrr(const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
const LatticeCell &L1 = Inputs.get(R2.Reg);
const LatticeCell &L2 = Inputs.get(R2.Reg);
@@ -1463,8 +1455,9 @@ bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1,
return !Result.isBottom();
}
-bool MachineConstEvaluator::evaluateORri(const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateORri(const RegSubRegPair &R1,
+ const APInt &A2, const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
if (A2 == 0)
return getCell(R1, Inputs, Result);
@@ -1499,8 +1492,10 @@ bool MachineConstEvaluator::evaluateORii(const APInt &A1,
return true;
}
-bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateXORrr(const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
LatticeCell LS1, LS2;
if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
@@ -1528,8 +1523,10 @@ bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1,
return !Result.isBottom();
}
-bool MachineConstEvaluator::evaluateXORri(const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateXORri(const RegSubRegPair &R1,
+ const APInt &A2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1561,8 +1558,10 @@ bool MachineConstEvaluator::evaluateXORii(const APInt &A1,
return true;
}
-bool MachineConstEvaluator::evaluateZEXTr(const RegisterSubReg &R1, unsigned Width,
- unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateZEXTr(const RegSubRegPair &R1,
+ unsigned Width, unsigned Bits,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1592,8 +1591,10 @@ bool MachineConstEvaluator::evaluateZEXTi(const APInt &A1, unsigned Width,
return true;
}
-bool MachineConstEvaluator::evaluateSEXTr(const RegisterSubReg &R1, unsigned Width,
- unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateSEXTr(const RegSubRegPair &R1,
+ unsigned Width, unsigned Bits,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1657,8 +1658,9 @@ bool MachineConstEvaluator::evaluateSEXTi(const APInt &A1, unsigned Width,
return true;
}
-bool MachineConstEvaluator::evaluateCLBr(const RegisterSubReg &R1, bool Zeros,
- bool Ones, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateCLBr(const RegSubRegPair &R1, bool Zeros,
+ bool Ones, const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1692,8 +1694,9 @@ bool MachineConstEvaluator::evaluateCLBi(const APInt &A1, bool Zeros,
return true;
}
-bool MachineConstEvaluator::evaluateCTBr(const RegisterSubReg &R1, bool Zeros,
- bool Ones, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateCTBr(const RegSubRegPair &R1, bool Zeros,
+ bool Ones, const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1727,9 +1730,11 @@ bool MachineConstEvaluator::evaluateCTBi(const APInt &A1, bool Zeros,
return true;
}
-bool MachineConstEvaluator::evaluateEXTRACTr(const RegisterSubReg &R1,
- unsigned Width, unsigned Bits, unsigned Offset, bool Signed,
- const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateEXTRACTr(const RegSubRegPair &R1,
+ unsigned Width, unsigned Bits,
+ unsigned Offset, bool Signed,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
assert(Bits+Offset <= Width);
LatticeCell LS1;
@@ -1785,9 +1790,10 @@ bool MachineConstEvaluator::evaluateEXTRACTi(const APInt &A1, unsigned Bits,
return true;
}
-bool MachineConstEvaluator::evaluateSplatr(const RegisterSubReg &R1,
- unsigned Bits, unsigned Count, const CellMap &Inputs,
- LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateSplatr(const RegSubRegPair &R1,
+ unsigned Bits, unsigned Count,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1835,8 +1841,8 @@ namespace {
bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs) override;
- bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
- LatticeCell &Result) override;
+ bool evaluate(const RegSubRegPair &R, const LatticeCell &SrcC,
+ LatticeCell &Result) override;
bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
SetVector<const MachineBasicBlock*> &Targets, bool &FallsThru)
override;
@@ -1850,8 +1856,8 @@ namespace {
const MachineOperand &MO);
void replaceWithNop(MachineInstr &MI);
- bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
- LatticeCell &Result);
+ bool evaluateHexRSEQ32(RegSubRegPair RL, RegSubRegPair RH,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs);
// This is suitable to be called for compare-and-jump instructions.
@@ -1924,14 +1930,14 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
return false;
unsigned Opc = MI.getOp...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/138637
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