[llvm] [RISCV] Add compress patterns for qc.extu and qc.mveqi (PR #138630)
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llvm-commits at lists.llvm.org
Mon May 5 23:27:39 PDT 2025
https://github.com/hchandel updated https://github.com/llvm/llvm-project/pull/138630
>From 4873b727a0646487c3806898727f24eb70d3cab4 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Mon, 5 May 2025 16:56:03 +0530
Subject: [PATCH 1/2] Add compress patterns for qc.extu and qc.mveqi
Change-Id: Id277974a325d22c1975bbab0b1ccf918938dc9aa
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 23 +++++++++++++++++++++
llvm/test/MC/RISCV/xqcibm-valid.s | 14 ++++++++++---
llvm/test/MC/RISCV/xqcicm-valid.s | 15 +++++++++++---
3 files changed, 46 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 89b0595bc21fc..9bdf29d7ee579 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -40,6 +40,13 @@ def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1Operand<5>";
let OperandType = "OPERAND_UIMM5_PLUS1";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
+ return MCOp.isBareSymbolRef();
+ }];
+
}
def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
@@ -48,6 +55,12 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1OperandGE<5,6>";
let OperandType = "OPERAND_UIMM5_GE6_PLUS1";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
+ return MCOp.isBareSymbolRef();
+ }];
}
def uimm5slist : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
@@ -1369,3 +1382,13 @@ def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
(SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
} // isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32]
+
+let Predicates = [HasVendorXqcicm, IsRV32] in {
+def : CompressPat<(QC_MVEQI GPRC:$rd, GPRC:$rd, 0, GPRC:$rs1),
+ (QC_C_MVEQZ GPRC:$rd, GPRC:$rs1)>;
+}
+
+let Predicates = [HasVendorXqcibm, IsRV32] in {
+def : CompressPat<(QC_EXTU GPRNoX0:$rd, GPRNoX0:$rd, uimm5ge6_plus1:$width, 0),
+ (QC_C_EXTU GPRNoX0:$rd, uimm5ge6_plus1:$width)>;
+}
diff --git a/llvm/test/MC/RISCV/xqcibm-valid.s b/llvm/test/MC/RISCV/xqcibm-valid.s
index 4e1db5db14332..e549d5fdfd7d2 100644
--- a/llvm/test/MC/RISCV/xqcibm-valid.s
+++ b/llvm/test/MC/RISCV/xqcibm-valid.s
@@ -1,11 +1,11 @@
# Xqcibm - Qualcomm uC Bit Manipulation Extension
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm -M no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcibm -M no-aliases --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcibm --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
@@ -118,6 +118,14 @@ qc.c.bexti x9, 8
# CHECK-ENC: encoding: [0x41,0x96]
qc.c.bseti x12, 16
-# CHECK-INST: qc.c.extu a5, 32
+# CHECK-NOALIAS: qc.c.extu a5, 32
+# CHECK-ALIAS: qc.extu a5, a5, 32, 0
# CHECK-ENC: encoding: [0xfe,0x17]
qc.c.extu x15, 32
+
+# Check that compress pattern for qc.extu works
+
+# CHECK-NOALIAS: qc.c.extu a1, 11
+# CHECK-ALIAS: qc.extu a1, a1, 11, 0
+# CHECK-ENC: encoding: [0xaa,0x15]
+qc.extu x11, x11, 11, 0
diff --git a/llvm/test/MC/RISCV/xqcicm-valid.s b/llvm/test/MC/RISCV/xqcicm-valid.s
index 428ce3aa5f496..f480a9e5fb007 100644
--- a/llvm/test/MC/RISCV/xqcicm-valid.s
+++ b/llvm/test/MC/RISCV/xqcicm-valid.s
@@ -1,16 +1,17 @@
# Xqcicm - Qualcomm uC Conditional Move Extension
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -M no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicm < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcicm -M no-aliases --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicm < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcicm --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# CHECK-INST: qc.c.mveqz s1, a0
+# CHECK-NOALIAS: qc.c.mveqz s1, a0
+# CHECK-ALIAS: qc.mveqi s1, s1, 0, a0
# CHECK-ENC: encoding: [0x06,0xad]
qc.c.mveqz x9, x10
@@ -121,3 +122,11 @@ qc.mvgeui x9, x10, 0, x12
# CHECK-INST: qc.mvgeui s1, a0, 31, a2
# CHECK-ENC: encoding: [0xdb,0x74,0xf5,0x65]
qc.mvgeui x9, x10, 31, x12
+
+# Check that compress pattern for qc.mveqi works
+
+# CHECK-NOALIAS: qc.c.mveqz s1, a2
+# CHECK-ALIAS: qc.mveqi s1, s1, 0, a2
+# CHECK-ENC: encoding: [0x06,0xae]
+qc.mveqi x9, x9, 0, x12
+
>From 80a58cd10ae282e9fc3bf59c227eb6b98f581052 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Mon, 5 May 2025 17:22:32 +0530
Subject: [PATCH 2/2] [RISCV] Add compress patterns for qc.extu and qc.mveqi
Change-Id: If45e95ffb225e058652f6528e46b5cb7b924832f
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 9bdf29d7ee579..58b6c08ad0d05 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -42,11 +42,10 @@ def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
let OperandType = "OPERAND_UIMM5_PLUS1";
let MCOperandPredicate = [{
int64_t Imm;
- if (MCOp.evaluateAsConstantImm(Imm))
- return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
- return MCOp.isBareSymbolRef();
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
}];
-
}
def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
@@ -57,9 +56,9 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
let OperandType = "OPERAND_UIMM5_GE6_PLUS1";
let MCOperandPredicate = [{
int64_t Imm;
- if (MCOp.evaluateAsConstantImm(Imm))
- return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
- return MCOp.isBareSymbolRef();
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
}];
}
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