[llvm] [AMDGPU][NFC] Add test for 64-bit lshr with shifts >=32 (PR #138281)

[Matt Arsenault via llvm-commits]

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@@ -27,7 +27,21 @@ define i64 @srl_metadata(i64 %arg0, ptr %arg1.ptr) {
   ret i64 %srl
 }
 
-; Shifted bits matter for exact shift.  Reduction must not be done.
+define amdgpu_ps i64 @srl_metadata_sgpr_return(i64 inreg %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: srl_metadata_sgpr_return:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    flat_load_dword v0, v[0:1]
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arsenm wrote:

Don't want the vector load. Pointer should also be inreg, and should make invariant addrspace(1) 

https://github.com/llvm/llvm-project/pull/138281