[llvm] [GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (PR #138574)

[Matt Arsenault via llvm-commits]

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@@ -119,6 +119,18 @@ static LegalizeMutation fewerEltsToSize64Vector(unsigned TypeIdx) {
   };
 }
 
+static LegalizeMutation breakCurrentEltsToSize32Or64(unsigned TypeIdx) {
+  return [=](const LegalityQuery &Query) {
+    const LLT Ty = Query.Types[TypeIdx];
+    const LLT EltTy = Ty.getElementType();
+    const int Size = Ty.getSizeInBits();
+    const int EltSize = EltTy.getSizeInBits();
+    const unsigned TargetEltSize = EltSize % 64 == 0 ? 64 : 32;
+    const unsigned NewNumElts = (Size + (TargetEltSize - 1)) / TargetEltSize;
+    return std::pair(TypeIdx, LLT::fixed_vector(NewNumElts, TargetEltSize));
+  };
+}
+
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arsenm wrote:

This rule looks overly complicated. I'd expect this to work as a consequence of hitting scalarize and then narrow with the existing rules, and this is probably working around a missing case in LegalizerHelper 

https://github.com/llvm/llvm-project/pull/138574