[llvm] 9350906 - Revert "ARM: Remove override of shouldRewriteCopySrc (#125219)"

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2025-05-05T22:08:48+02:00
New Revision: 93509064a61973c2e696607e4802f73c32dbac83

URL: https://github.com/llvm/llvm-project/commit/93509064a61973c2e696607e4802f73c32dbac83
DIFF: https://github.com/llvm/llvm-project/commit/93509064a61973c2e696607e4802f73c32dbac83.diff

LOG: Revert "ARM: Remove override of shouldRewriteCopySrc (#125219)"

This reverts commit 9d90f8ba7113fd9c7b2662682ad94b744ed2b78c.

Test fails the machine verifier. There's a bug somewhere, the
unrepresentable cases should be avoided by the default logic.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
    llvm/test/CodeGen/ARM/shouldRewriteCopySrc.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 82941b5bcd4c7..bc20daf0cfbbc 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -961,3 +961,17 @@ bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
   }
   return false;
 }
+
+bool ARMBaseRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
+                                               unsigned DefSubReg,
+                                               const TargetRegisterClass *SrcRC,
+                                               unsigned SrcSubReg) const {
+  // We can't extract an SPR from an arbitary DPR (as opposed to a DPR_VFP2).
+  if (DefRC == &ARM::SPRRegClass && DefSubReg == 0 &&
+      SrcRC == &ARM::DPRRegClass &&
+      (SrcSubReg == ARM::ssub_0 || SrcSubReg == ARM::ssub_1))
+    return false;
+
+  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
+                                                  SrcRC, SrcSubReg);
+}

diff  --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
index 71fe2d2b70828..69e10ac2a54d2 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -159,6 +159,11 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
                       const TargetRegisterClass *NewRC,
                       LiveIntervals &LIS) const override;
 
+  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
+                            unsigned DefSubReg,
+                            const TargetRegisterClass *SrcRC,
+                            unsigned SrcSubReg) const override;
+
   int getSEHRegNum(unsigned i) const { return getEncodingValue(i); }
 };
 

diff  --git a/llvm/test/CodeGen/ARM/shouldRewriteCopySrc.ll b/llvm/test/CodeGen/ARM/shouldRewriteCopySrc.ll
index 2bf8f29eccb40..e653aaa316fed 100644
--- a/llvm/test/CodeGen/ARM/shouldRewriteCopySrc.ll
+++ b/llvm/test/CodeGen/ARM/shouldRewriteCopySrc.ll
@@ -12,8 +12,8 @@ define float @shouldRewriteCopySrc(double %arg) #0 {
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    vmov.f64 d0, d16
-; CHECK-NEXT:    @ kill: def $s0 killed $s0 killed $d0
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    bx lr
 bb: