[llvm] [RISCV] Add scheduler definitions for SpacemiT-X60 (PR #137343)

[Philip Reames via llvm-commits]

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@@ -0,0 +1,332 @@
+//=- RISCVSchedSpacemitX60.td - Spacemit X60 Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// Scheduler model for the SpacemiT-X60 processor based on documentation of the
+// C908 and experiments on real hardware (bpi-f3).
+//
+//===----------------------------------------------------------------------===//
+
+def SpacemitX60Model : SchedMachineModel {
+  let IssueWidth        = 2; // dual-issue
+  let MicroOpBufferSize = 0; // in-order
+  let LoadLatency       = 5; // worse case: >= 3
+  let MispredictPenalty = 9; // nine-stage
+
+  let CompleteModel = 0;
+
+  let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr];
+}
+
+let SchedModel = SpacemitX60Model in {
+
+//===----------------------------------------------------------------------===//
+// Define processor resources for Spacemit-X60
+
+// Information gathered from the C908 user manual:
+let BufferSize = 0 in {
+  // The LSU supports dual issue for scalar store/load instructions
+  def SMX60_LS : ProcResource<2>;
+
+  // An IEU can decode and issue two instructions at the same time
+  def SMX60_IEU : ProcResource<2>;
+
+  def SMX60_FP : ProcResource<1>;
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preames wrote:

As a follow up (as in, *not* in this patch), it would be good to explore this further.  

https://github.com/llvm/llvm-project/pull/137343