[llvm] [NFC][TableGen] Code cleanup in CodeGenRegister (PR #137994)

[Rahul Joshi via llvm-commits]

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@@ -975,29 +948,28 @@ static bool testSubClass(const CodeGenRegisterClass *A,
 /// ordering that arranges all register classes before their sub-classes.
 ///
 /// Register classes with the same registers, spill size, and alignment form a
-/// clique.  They will be ordered alphabetically.
+/// clique. They will be ordered alphabetically.
 ///
-static bool TopoOrderRC(const CodeGenRegisterClass &PA,
-                        const CodeGenRegisterClass &PB) {
-  auto *A = &PA;
-  auto *B = &PB;
-  if (A == B)
-    return false;
-
-  if (A->RSI < B->RSI)
-    return true;
-  if (A->RSI != B->RSI)
+static bool TopoOrderRC(const CodeGenRegisterClass &A,
+                        const CodeGenRegisterClass &B) {
+  if (&A == &B)
     return false;
 
-  // Order by descending set size.  Note that the classes' allocation order may
-  // not have been computed yet.  The Members set is always vaild.
-  if (A->getMembers().size() > B->getMembers().size())
-    return true;
-  if (A->getMembers().size() < B->getMembers().size())
-    return false;
+  constexpr size_t SIZET_MAX = std::numeric_limits<size_t>::max();
 
-  // Finally order by name as a tie breaker.
-  return StringRef(A->getName()) < B->getName();
+  // sort in the following order:
+  // (a) first by register size in ascending order.
+  // (b) then by set size in descending order.
+  // (c) finally, by name as a tie breaker.
+  //
+  // For set size, Note that the classes' allocation order may not have been
+  // computed yet. The Members set is always vaild. Also, Since we use
+  // std::tie() < operator for ordering, we can achieve the desceding set size
+  // ordering by using (SIZET_MAX - set_size) in the tie.
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jurahul wrote:

Done.

https://github.com/llvm/llvm-project/pull/137994