[llvm] [AMDGPU] Eliminate unnecessary packing in wider f16 vectors for sdwa/opsel-able instruction (PR #137137)

[Vikash Gupta via llvm-commits]

vg0204 wrote:

@Pierre-vh do you have anything to comment on added MIR test showcasing exact MIR pattern handled via this optimization?

https://github.com/llvm/llvm-project/pull/137137