[llvm] [AMDGPU] Extend test coverage for cross RC register coalescing (PR #132137)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm approved this pull request.

LGTM but I think you just got hit by one of the recent tablegen changes which shifted the register class numbers around. You'll probably need to rebase and adjust the numbers 

https://github.com/llvm/llvm-project/pull/132137