[llvm] [X86][APX] Fix the assertion of NF instruction with relocation (PR #138500)
Feng Zou via llvm-commits
llvm-commits at lists.llvm.org
Mon May 5 06:22:52 PDT 2025
https://github.com/fzou1 updated https://github.com/llvm/llvm-project/pull/138500
>From d34951efad0aec4f9504f8d54725168c57dcb26f Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Mon, 5 May 2025 17:54:21 +0800
Subject: [PATCH 1/2] [X86][APX] Fix the assertion of NF instruction with
relocation
The assertion should be raised only for the NF instructions with GOTTPOFF
relocation.
---
.../lib/Target/X86/X86SuppressAPXForReloc.cpp | 10 +-
.../apx/check-nf-in-suppress-reloc-pass.ll | 96 +++++++++++++++++++
2 files changed, 104 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll
diff --git a/llvm/lib/Target/X86/X86SuppressAPXForReloc.cpp b/llvm/lib/Target/X86/X86SuppressAPXForReloc.cpp
index fe7a49ab4771d..d40995cb1786d 100644
--- a/llvm/lib/Target/X86/X86SuppressAPXForReloc.cpp
+++ b/llvm/lib/Target/X86/X86SuppressAPXForReloc.cpp
@@ -155,8 +155,14 @@ static bool handleNDDOrNFInstructions(MachineFunction &MF,
switch (Opcode) {
case X86::ADD64rm_NF:
case X86::ADD64mr_NF_ND:
- case X86::ADD64rm_NF_ND:
- llvm_unreachable("Unexpected NF instruction!");
+ case X86::ADD64rm_NF_ND: {
+ int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
+ X86II::getOperandBias(MI.getDesc());
+ const MachineOperand &MO = MI.getOperand(X86::AddrDisp + MemOpNo);
+ if (MO.getTargetFlags() == X86II::MO_GOTTPOFF)
+ llvm_unreachable("Unexpected NF instruction!");
+ break;
+ }
case X86::ADD64rm_ND: {
int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
X86II::getOperandBias(MI.getDesc());
diff --git a/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll b/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll
new file mode 100644
index 0000000000000..80886ee96cb38
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64 -mattr=+nf -verify-machineinstrs | FileCheck %s
+
+; This is to check no assertion raised in X86 Suppress APX for Relocation pass
+; if there is a NF instruction
+
+define fastcc void @foo(i32 %0, i1 %or.cond) {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 56
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 64
+; CHECK-NEXT: .cfi_offset %rbx, -56
+; CHECK-NEXT: .cfi_offset %r12, -48
+; CHECK-NEXT: .cfi_offset %r13, -40
+; CHECK-NEXT: .cfi_offset %r14, -32
+; CHECK-NEXT: .cfi_offset %r15, -24
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movl %esi, %ebx
+; CHECK-NEXT: movslq %edi, %r15
+; CHECK-NEXT: leaq (,%r15,4), %rax
+; CHECK-NEXT: leaq (%rax,%rax,4), %r14
+; CHECK-NEXT: movl %r15d, %r12d
+; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: jmp .LBB0_1
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB0_3: # %if.end41
+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT: leaq (%r12,%rbp), %rdi
+; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: movq %r14, %rdx
+; CHECK-NEXT: callq *%r13
+; CHECK-NEXT: incq %rbp
+; CHECK-NEXT: addq $20, %r14
+; CHECK-NEXT: .LBB0_1: # %for.body30
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: testb $1, %bl
+; CHECK-NEXT: je .LBB0_3
+; CHECK-NEXT: # %bb.2: # %if.then37
+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT: movq %r15, %rax
+; CHECK-NEXT: addq %rbp, %rax
+; CHECK-NEXT: movq 0, %rax
+; CHECK-NEXT: {nf} addq %r15, %rax
+; CHECK-NEXT: movb $0, (%rbp,%rax)
+; CHECK-NEXT: jmp .LBB0_3
+entry:
+ %1 = sext i32 %0 to i64
+ br label %for.body30
+
+for.body30: ; preds = %if.end41, %entry
+ %indvars.iv = phi i64 [ %1, %entry ], [ %indvars.iv.next, %if.end41 ]
+ %.pre88 = trunc i64 %indvars.iv to i32
+ br label %if.end16.i
+
+if.then9.i: ; No predecessors!
+ call fastcc void null(ptr null, i32 %.pre88)
+ br label %if.end16.i
+
+if.end16.i: ; preds = %if.then9.i, %for.body30
+ br i1 %or.cond, label %if.then37, label %if.end41
+
+if.then37: ; preds = %if.end16.i
+ %2 = load ptr, ptr null, align 8
+ %arrayidx.i = getelementptr i8, ptr %2, i64 %indvars.iv
+ store i8 0, ptr %arrayidx.i, align 1
+ %3 = icmp eq i64 %indvars.iv, 0
+ br i1 %3, label %if.end41, label %if.then.i65
+
+if.then.i65: ; preds = %if.then37
+ %arraydecay.i = getelementptr [5 x float], ptr null, i64 %indvars.iv, i64 -5
+ %4 = call <5 x float> @llvm.masked.load.v5f32.p0(ptr %arraydecay.i, i32 1, <5 x i1> zeroinitializer, <5 x float> zeroinitializer)
+ br label %if.end41
+
+if.end41: ; preds = %if.then.i65, %if.then37, %if.end16.i
+ %arraydecay44 = getelementptr [5 x float], ptr null, i64 %indvars.iv, i64 0
+ call fastcc void null(i32 %.pre88, i32 0, ptr %arraydecay44)
+ %indvars.iv.next = add i64 %indvars.iv, 1
+ %cmp29 = icmp slt i64 %indvars.iv, 0
+ br label %for.body30
+}
+
+declare <5 x float> @llvm.masked.load.v5f32.p0(ptr captures(none), i32 immarg, <5 x i1>, <5 x float>)
>From 7d036ebb0d61308ced083d785e9e5b35c262be76 Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Mon, 5 May 2025 20:31:32 +0800
Subject: [PATCH 2/2] Add nounwind attribute to remove cfi instructions.
---
.../X86/apx/check-nf-in-suppress-reloc-pass.ll | 15 +--------------
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll b/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll
index 80886ee96cb38..3a2c954e37077 100644
--- a/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll
+++ b/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll
@@ -4,29 +4,16 @@
; This is to check no assertion raised in X86 Suppress APX for Relocation pass
; if there is a NF instruction
-define fastcc void @foo(i32 %0, i1 %or.cond) {
+define fastcc void @foo(i32 %0, i1 %or.cond) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbp
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %r15
-; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: pushq %r14
-; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: pushq %r13
-; CHECK-NEXT: .cfi_def_cfa_offset 40
; CHECK-NEXT: pushq %r12
-; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: .cfi_def_cfa_offset 56
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 64
-; CHECK-NEXT: .cfi_offset %rbx, -56
-; CHECK-NEXT: .cfi_offset %r12, -48
-; CHECK-NEXT: .cfi_offset %r13, -40
-; CHECK-NEXT: .cfi_offset %r14, -32
-; CHECK-NEXT: .cfi_offset %r15, -24
-; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movslq %edi, %r15
; CHECK-NEXT: leaq (,%r15,4), %rax
More information about the llvm-commits
mailing list