[llvm] 8f3fc72 - [AMDGPU] Use Reg32Types for move-immediate patterns (#138422)

[via llvm-commits]

Author: Jay Foad
Date: 2025-05-05T12:18:46+01:00
New Revision: 8f3fc7241145ab164dd7859e4349c2ff62619b94

URL: https://github.com/llvm/llvm-project/commit/8f3fc7241145ab164dd7859e4349c2ff62619b94
DIFF: https://github.com/llvm/llvm-project/commit/8f3fc7241145ab164dd7859e4349c2ff62619b94.diff

LOG: [AMDGPU] Use Reg32Types for move-immediate patterns (#138422)

This just avoids having another copy of the list of valid 32-bit pointer
types.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index f5c6d47369781..dea20e2d84d7b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2270,16 +2270,18 @@ def : GCNPat <
 
 // FIXME: Remove VGPRImm. Should be inferrable from register bank.
 
-foreach vt = [i32, p3, p5, p6, p2] in {
-  def : GCNPat <
-    (VGPRImm<(vt imm)>:$imm),
-    (V_MOV_B32_e32 imm:$imm)
-  >;
+foreach vt = Reg32Types.types in {
+  if !and(!not(vt.isVector), !not(vt.isFP)) then {
+    def : GCNPat <
+      (VGPRImm<(vt imm)>:$imm),
+      (V_MOV_B32_e32 imm:$imm)
+    >;
 
-  def : GCNPat <
-    (vt imm:$imm),
-    (S_MOV_B32 imm:$imm)
-  >;
+    def : GCNPat <
+      (vt imm:$imm),
+      (S_MOV_B32 imm:$imm)
+    >;
+  }
 }
 
 // FIXME: The register bank of the frame index should depend on the