[llvm] [llvm] Remove unused local variables (NFC) (PR #138478)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 4 16:25:36 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-sparc
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/138478.diff
18 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (-3)
- (modified) llvm/lib/LTO/LTO.cpp (-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (-4)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (-2)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (-1)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (-2)
- (modified) llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (-1)
- (modified) llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp (-1)
- (modified) llvm/lib/Target/BPF/BPFMIChecking.cpp (-1)
- (modified) llvm/lib/Target/Hexagon/HexagonVExtract.cpp (-1)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp (-1)
- (modified) llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (-1)
- (modified) llvm/lib/Target/Sparc/SparcISelLowering.cpp (-3)
- (modified) llvm/lib/Target/VE/VEISelDAGToDAG.cpp (-1)
- (modified) llvm/lib/Target/X86/X86ISelDAGToDAG.cpp (-2)
- (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (-3)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 713bf4177b5f7..00c6f90e1c864 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12356,7 +12356,6 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) {
SDValue Chain = MST->getChain();
SDValue Value = MST->getValue();
SDValue Ptr = MST->getBasePtr();
- SDLoc DL(N);
// Zap masked stores with a zero mask.
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode()))
@@ -12559,7 +12558,6 @@ SDValue DAGCombiner::visitMGATHER(SDNode *N) {
SDValue DAGCombiner::visitMLOAD(SDNode *N) {
MaskedLoadSDNode *MLD = cast<MaskedLoadSDNode>(N);
SDValue Mask = MLD->getMask();
- SDLoc DL(N);
// Zap masked loads with a zero mask.
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode()))
@@ -23725,7 +23723,6 @@ SDValue DAGCombiner::reduceBuildVecTruncToBitCast(SDNode *N) {
if (!DAG.getDataLayout().isLittleEndian())
return SDValue();
- SDLoc DL(N);
EVT OutScalarTy = VT.getScalarType();
uint64_t ScalarTypeBitsize = OutScalarTy.getSizeInBits();
diff --git a/llvm/lib/LTO/LTO.cpp b/llvm/lib/LTO/LTO.cpp
index 613e2d971c8b8..f82769212ccdd 100644
--- a/llvm/lib/LTO/LTO.cpp
+++ b/llvm/lib/LTO/LTO.cpp
@@ -634,7 +634,6 @@ void LTO::addModuleToGlobalRes(ArrayRef<InputFile::Symbol> Syms,
auto *ResI = Res.begin();
auto *ResE = Res.end();
(void)ResE;
- const Triple TT(RegularLTO.CombinedModule->getTargetTriple());
for (const InputFile::Symbol &Sym : Syms) {
assert(ResI != ResE);
SymbolResolution Res = *ResI++;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 60288606d62b5..1c889d67c81e0 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3099,7 +3099,6 @@ AArch64TargetLowering::EmitDynamicProbedAlloc(MachineInstr &MI,
MachineBasicBlock *MBB) const {
MachineFunction &MF = *MBB->getParent();
MachineBasicBlock::iterator MBBI = MI.getIterator();
- DebugLoc DL = MBB->findDebugLoc(MBBI);
const AArch64InstrInfo &TII =
*MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
Register TargetReg = MI.getOperand(0).getReg();
@@ -11953,7 +11952,6 @@ SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
EVT VT = getPointerTy(DAG.getDataLayout());
- SDLoc DL(Op);
int FI = MFI.CreateFixedObject(4, 0, false);
return DAG.getFrameIndex(FI, VT);
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 536bf0c208752..3676cb6925b8a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -997,7 +997,6 @@ void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
}
void AMDGPUDAGToDAGISel::SelectAddcSubb(SDNode *N) {
- SDLoc DL(N);
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue CI = N->getOperand(2);
@@ -1050,7 +1049,6 @@ void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
}
void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
- SDLoc SL(N);
// src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
SDValue Ops[10];
@@ -1071,7 +1069,6 @@ void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
}
void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
- SDLoc SL(N);
// src0_modifiers, src0, src1_modifiers, src1, clamp, omod
SDValue Ops[8];
@@ -1086,7 +1083,6 @@ void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
// We need to handle this here because tablegen doesn't support matching
// instructions with multiple outputs.
void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
- SDLoc SL(N);
EVT VT = N->getValueType(0);
assert(VT == MVT::f32 || VT == MVT::f64);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 8822ae29e063e..2ea94745860c3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2629,8 +2629,6 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
assert(MRI.getRegBankOrNull(DstReg) == &AMDGPU::VGPRRegBank &&
"The destination operand should be in vector registers.");
- DebugLoc DL = MI.getDebugLoc();
-
// Extract the lower subregister from the first operand.
Register Op0L = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ccdc3223ea983..e2584a867cefc 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11807,7 +11807,6 @@ static unsigned getBasePtrIndex(const MemSDNode *N) {
SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
- SDLoc SL(N);
unsigned PtrIdx = getBasePtrIndex(N);
SDValue Ptr = N->getOperand(PtrIdx);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 03364d9025208..878f6878c2b60 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10624,7 +10624,6 @@ SDValue ARMTargetLowering::LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const {
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
EVT VT = getPointerTy(DAG.getDataLayout());
- SDLoc DL(Op);
int FI = MFI.CreateFixedObject(4, 0, false);
return DAG.getFrameIndex(FI, VT);
}
@@ -12453,7 +12452,6 @@ static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget,
MachineInstr &MI, const SDNode *Node) {
bool isThumb1 = Subtarget->isThumb1Only();
- DebugLoc DL = MI.getDebugLoc();
MachineFunction *MF = MI.getParent()->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
MachineInstrBuilder MIB(*MF, MI);
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 956fc9680ee33..48ad8a8994ae8 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -11846,7 +11846,6 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
return Error(L, "Unknown arch name");
bool WasThumb = isThumb();
- Triple T;
MCSubtargetInfo &STI = copySTI();
STI.setDefaultFeatures("", /*TuneCPU*/ "",
("+" + ARM::getArchName(ID)).str());
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index a8927d834630e..da861227d1acd 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -571,7 +571,6 @@ void AVRDAGToDAGISel::Select(SDNode *N) {
bool AVRDAGToDAGISel::trySelect(SDNode *N) {
unsigned Opcode = N->getOpcode();
- SDLoc DL(N);
switch (Opcode) {
// Nodes we fully handle.
diff --git a/llvm/lib/Target/BPF/BPFMIChecking.cpp b/llvm/lib/Target/BPF/BPFMIChecking.cpp
index 4f5dfafda9efe..5668e85377a2a 100644
--- a/llvm/lib/Target/BPF/BPFMIChecking.cpp
+++ b/llvm/lib/Target/BPF/BPFMIChecking.cpp
@@ -159,7 +159,6 @@ void BPFMIPreEmitChecking::processAtomicInsts() {
LLVM_DEBUG(MI.dump());
if (hasLiveDefs(MI, TRI)) {
- DebugLoc Empty;
const DebugLoc &DL = MI.getDebugLoc();
const Function &F = MF->getFunction();
F.getContext().diagnose(DiagnosticInfoUnsupported{
diff --git a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
index 42a65eba7b88c..3b3d25d4c22c5 100644
--- a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
@@ -161,7 +161,6 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
assert(ExtI->getOperand(1).getReg() == VecR);
MachineBasicBlock &ExtB = *ExtI->getParent();
- DebugLoc DL = ExtI->getDebugLoc();
Register BaseR = EmitAddr(ExtB, ExtI, ExtI->getDebugLoc(), FI,
SR == 0 ? 0 : VecSize/2);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 1383302059910..802b2cbb14226 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2549,7 +2549,6 @@ static SDValue checkIntrinsicImmArg(SDValue Op, unsigned ImmOp,
SDValue
LoongArchTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
- SDLoc DL(Op);
switch (Op.getConstantOperandVal(0)) {
default:
return SDValue(); // Don't custom lower most intrinsics.
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 37882de7b3046..3769aae7b620f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -2709,7 +2709,6 @@ static SDValue LowerTcgen05St(SDValue Op, SelectionDAG &DAG) {
static SDValue LowerIntrinsicVoid(SDValue Op, SelectionDAG &DAG) {
SDNode *N = Op.getNode();
SDValue Intrin = N->getOperand(1);
- SDLoc DL(N);
// Get the intrinsic ID
unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 0907239153226..7147506bbd89b 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -2975,7 +2975,6 @@ SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
if (!WideRes)
return nullptr;
- SDLoc dl(N);
bool Input32Bit = WideRes.getValueType() == MVT::i32;
bool Output32Bit = N->getValueType(0) == MVT::i32;
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 0b98327d53434..6c3a56d445c44 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2618,7 +2618,6 @@ static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
const SparcTargetLowering &TLI,
bool hasHardQuad) {
- SDLoc dl(Op);
EVT VT = Op.getValueType();
// Expand if it does not involve f128 or the target has support for
@@ -2639,7 +2638,6 @@ static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
const SparcTargetLowering &TLI,
bool hasHardQuad) {
- SDLoc dl(Op);
EVT OpVT = Op.getOperand(0).getValueType();
assert(OpVT == MVT::i32 || OpVT == MVT::i64);
@@ -3162,7 +3160,6 @@ static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
unsigned IntNo = Op.getConstantOperandVal(0);
- SDLoc dl(Op);
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::thread_pointer: {
diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
index 85bb69cf33fda..4e1bac0e91734 100644
--- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
@@ -249,7 +249,6 @@ bool VEDAGToDAGISel::matchADDRri(SDValue Addr, SDValue &Base, SDValue &Offset) {
}
void VEDAGToDAGISel::Select(SDNode *N) {
- SDLoc dl(N);
if (N->isMachineOpcode()) {
N->setNodeId(-1);
return; // Already selected.
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 01118beb9cf5e..32c7d2bfea6c2 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2512,7 +2512,6 @@ SDValue X86DAGToDAGISel::matchIndexRecursively(SDValue N,
bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
unsigned Depth) {
- SDLoc dl(N);
LLVM_DEBUG({
dbgs() << "MatchAddress: ";
AM.dump(CurDAG);
@@ -2903,7 +2902,6 @@ bool X86DAGToDAGISel::matchAddressBase(SDValue N, X86ISelAddressMode &AM) {
bool X86DAGToDAGISel::matchVectorAddressRecursively(SDValue N,
X86ISelAddressMode &AM,
unsigned Depth) {
- SDLoc dl(N);
LLVM_DEBUG({
dbgs() << "MatchVectorAddress: ";
AM.dump(CurDAG);
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index b1c832ac9aeb0..232983c9e5a90 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -6592,7 +6592,6 @@ struct VarArgPowerPC64Helper : public VarArgHelperBase {
// Instrument va_start.
// Copy va_list shadow from the backup copy of the TLS contents.
- Triple TargetTriple(F.getParent()->getTargetTriple());
for (CallInst *OrigInst : VAStartInstrumentationList) {
NextNodeIRBuilder IRB(OrigInst);
Value *VAListTag = OrigInst->getArgOperand(0);
@@ -6625,7 +6624,6 @@ struct VarArgPowerPC32Helper : public VarArgHelperBase {
void visitCallBase(CallBase &CB, IRBuilder<> &IRB) override {
unsigned VAArgBase;
- Triple TargetTriple(F.getParent()->getTargetTriple());
// Parameter save area is 8 bytes from frame pointer in PPC32
VAArgBase = 8;
unsigned VAArgOffset = VAArgBase;
@@ -6730,7 +6728,6 @@ struct VarArgPowerPC32Helper : public VarArgHelperBase {
// Instrument va_start.
// Copy va_list shadow from the backup copy of the TLS contents.
- Triple TargetTriple(F.getParent()->getTargetTriple());
for (CallInst *OrigInst : VAStartInstrumentationList) {
NextNodeIRBuilder IRB(OrigInst);
Value *VAListTag = OrigInst->getArgOperand(0);
``````````
</details>
https://github.com/llvm/llvm-project/pull/138478
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