[llvm] 1d95548 - Revert "[CodeGen] Use range-based for loops (NFC) (#138434)"
Nico Weber via llvm-commits
llvm-commits at lists.llvm.org
Sun May 4 14:37:00 PDT 2025
Author: Nico Weber
Date: 2025-05-04T17:36:52-04:00
New Revision: 1d955489c3c2fc2da89826a5cd6bf7954cf133b7
URL: https://github.com/llvm/llvm-project/commit/1d955489c3c2fc2da89826a5cd6bf7954cf133b7
DIFF: https://github.com/llvm/llvm-project/commit/1d955489c3c2fc2da89826a5cd6bf7954cf133b7.diff
LOG: Revert "[CodeGen] Use range-based for loops (NFC) (#138434)"
This reverts commit a9699a334bc9666570418a3bed9520bcdc21518b.
Breaks CodeGen/AMDGPU/collapse-endcf.ll in several configs
(sanitizer builds; macOS; possibly more), see comments on
https://github.com/llvm/llvm-project/pull/138434
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
llvm/lib/CodeGen/MachineCSE.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index a3d973f98e993..908524313030f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1114,8 +1114,8 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
MaskTy = LLT::scalar(PtrTy.getSizeInBits());
else {
// Ensure that the type will fit the mask value.
- for (const SwitchCG::BitTestCase &Case : B.Cases) {
- if (!isUIntN(SwitchOpTy.getSizeInBits(), Case.Mask)) {
+ for (unsigned I = 0, E = B.Cases.size(); I != E; ++I) {
+ if (!isUIntN(SwitchOpTy.getSizeInBits(), B.Cases[I].Mask)) {
// Switch table case range are encoded into series of masks.
// Just use pointer type, it's guaranteed to fit.
MaskTy = LLT::scalar(PtrTy.getSizeInBits());
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index d6db4594861cf..a7e730eeff5ab 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -5498,8 +5498,9 @@ LegalizerHelper::fewerElementsBitcast(MachineInstr &MI, unsigned int TypeIdx,
// Build new smaller bitcast instructions
// Not supporting Leftover types for now but will have to
- for (Register Reg : SrcVRegs)
- BitcastVRegs.push_back(MIRBuilder.buildBitcast(NarrowTy, Reg).getReg(0));
+ for (unsigned i = 0; i < SrcVRegs.size(); i++)
+ BitcastVRegs.push_back(
+ MIRBuilder.buildBitcast(NarrowTy, SrcVRegs[i]).getReg(0));
MIRBuilder.buildMergeLikeInstr(DstReg, BitcastVRegs);
MI.eraseFromParent();
@@ -7378,8 +7379,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerTRUNC(MachineInstr &MI) {
InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits() * 2);
else
InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits());
- for (Register &Src : SplitSrcs)
- Src = MIRBuilder.buildTrunc(InterTy, Src).getReg(0);
+ for (unsigned I = 0; I < SplitSrcs.size(); ++I) {
+ SplitSrcs[I] = MIRBuilder.buildTrunc(InterTy, SplitSrcs[I]).getReg(0);
+ }
// Combine the new truncates into one vector
auto Merge = MIRBuilder.buildMergeLikeInstr(
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 5d6e7f1e67a4e..6bbd130fa7a9e 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -2588,7 +2588,8 @@ void InstrRefBasedLDV::placeMLocPHIs(
auto CollectPHIsForLoc = [&](LocIdx L) {
// Collect the set of defs.
SmallPtrSet<MachineBasicBlock *, 32> DefBlocks;
- for (MachineBasicBlock *MBB : OrderToBB) {
+ for (unsigned int I = 0; I < OrderToBB.size(); ++I) {
+ MachineBasicBlock *MBB = OrderToBB[I];
const auto &TransferFunc = MLocTransfer[MBB->getNumber()];
if (TransferFunc.contains(L))
DefBlocks.insert(MBB);
@@ -3799,7 +3800,8 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF,
// To mirror old LiveDebugValues, enumerate variables in RPOT order. Otherwise
// the order is unimportant, it just has to be stable.
unsigned VarAssignCount = 0;
- for (MachineBasicBlock *MBB : OrderToBB) {
+ for (unsigned int I = 0; I < OrderToBB.size(); ++I) {
+ auto *MBB = OrderToBB[I];
auto *VTracker = &vlocs[MBB->getNumber()];
// Collect each variable with a DBG_VALUE in this block.
for (auto &idx : VTracker->Vars) {
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index bebdead5ecb89..6d14509c5934f 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -325,8 +325,9 @@ bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
}
// Finally, add all defs to PhysRefs as well.
- for (const auto &Def : PhysDefs)
- for (MCRegAliasIterator AI(Def.second, TRI, true); AI.isValid(); ++AI)
+ for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
+ for (MCRegAliasIterator AI(PhysDefs[i].second, TRI, true); AI.isValid();
+ ++AI)
PhysRefs.insert(*AI);
return !PhysRefs.empty();
@@ -347,8 +348,9 @@ bool MachineCSEImpl::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
return false;
- for (const auto &PhysDef : PhysDefs) {
- if (MRI->isAllocatable(PhysDef.second) || MRI->isReserved(PhysDef.second))
+ for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
+ if (MRI->isAllocatable(PhysDefs[i].second) ||
+ MRI->isReserved(PhysDefs[i].second))
// Avoid extending live range of physical registers if they are
//allocatable or reserved.
return false;
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index 39d0f8613a400..83a9c0d738394 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -321,11 +321,12 @@ void RenameIndependentSubregs::computeMainRangesFixFlags(
// Search for "PHI" value numbers in the subranges. We must find a live
// value in each predecessor block, add an IMPLICIT_DEF where it is
// missing.
- for (const VNInfo *VNI : SR.valnos) {
- if (VNI->isUnused() || !VNI->isPHIDef())
+ for (unsigned I = 0; I < SR.valnos.size(); ++I) {
+ const VNInfo &VNI = *SR.valnos[I];
+ if (VNI.isUnused() || !VNI.isPHIDef())
continue;
- SlotIndex Def = VNI->def;
+ SlotIndex Def = VNI.def;
MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(Def);
for (MachineBasicBlock *PredMBB : MBB.predecessors()) {
SlotIndex PredEnd = Indexes.getMBBEndIdx(PredMBB);
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index a521a82e24d6b..30f65bde142d2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -360,8 +360,8 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
DelDeps.push_back(std::make_pair(SuccSU, D));
}
}
- for (const auto &Dep : DelDeps)
- RemovePred(Dep.first, Dep.second);
+ for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
+ RemovePred(DelDeps[i].first, DelDeps[i].second);
++NumDups;
return NewSU;
@@ -395,8 +395,8 @@ void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
DelDeps.push_back(std::make_pair(SuccSU, Succ));
}
}
- for (const auto &Dep : DelDeps) {
- RemovePred(Dep.first, Dep.second);
+ for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
+ RemovePred(DelDeps[i].first, DelDeps[i].second);
}
SDep FromDep(SU, SDep::Data, Reg);
FromDep.setLatency(SU->Latency);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 7030f0a926a33..881b1536a131f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3161,8 +3161,8 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
if (!TLI.isTypeLegal(VT)) {
UsePtrType = true;
} else {
- for (const BitTestCase &Case : B.Cases)
- if (!isUIntN(VT.getSizeInBits(), Case.Mask)) {
+ for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
+ if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
// Switch table case range are encoded into series of masks.
// Just use pointer type, it's guaranteed to fit.
UsePtrType = true;
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