[llvm] [Target] Remove unused local variables (NFC) (PR #138443)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 4 00:53:13 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/138443.diff
19 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (-2)
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp (-1)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp (-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp (-3)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (-1)
- (modified) llvm/lib/Target/AMDGPU/R600ISelLowering.cpp (-1)
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (-1)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (-1)
- (modified) llvm/lib/Target/ARM/ARMFrameLowering.cpp (-1)
- (modified) llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp (-1)
- (modified) llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (-1)
- (modified) llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp (-1)
- (modified) llvm/lib/Target/Mips/MipsCallLowering.cpp (-4)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp (-2)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp (-1)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (-2)
- (modified) llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp (-1)
- (modified) llvm/lib/Target/X86/X86LowerAMXType.cpp (-1)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a62aa443983e1..60288606d62b5 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7974,7 +7974,6 @@ SDValue AArch64TargetLowering::LowerFormalArguments(
assert(Chain.getOpcode() == ISD::EntryToken && "Unexpected Chain value");
SDValue Glue = Chain.getValue(1);
- SmallVector<SDValue, 16> ArgValues;
unsigned ExtraArgLocs = 0;
for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i - ExtraArgLocs];
@@ -18253,7 +18252,6 @@ static SDValue performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG,
return VecReduceAdd16;
// Generate the remainder Dot operation that is multiple of 8.
- SmallVector<SDValue, 4> SDotVec8;
SDValue Zeros = DAG.getConstant(0, DL, MVT::v2i32);
SDValue Vec8Op0 =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, A.getOperand(0),
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 52b362875b4ef..9f242bb29f704 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -1192,7 +1192,6 @@ bool AArch64RegisterInfo::getRegAllocationHints(
// operands. Look for a valid starting register for the group.
for (unsigned I = 0; I < StridedOrder.size(); ++I) {
MCPhysReg Reg = StridedOrder[I];
- SmallVector<MCPhysReg> Regs;
// If the FORM_TRANSPOSE nodes use the ZPRMul classes, the starting
// register of the first load should be a multiple of 2 or 4.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index cc607e863d190..3e8c166bd08b0 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -479,7 +479,6 @@ void AArch64TargetELFStreamer::finish() {
}
if (Syms.size() != NumSyms) {
SmallVector<const MCSymbol *, 0> NewSyms;
- DenseMap<MCSection *, size_t> Cnt;
Syms.truncate(NumSyms);
// Find the last symbol index for each candidate section.
for (auto [I, Sym] : llvm::enumerate(Syms)) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index a15f193549936..e977b9069173e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -1539,8 +1539,6 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
}
// Do the actual argument marshalling.
- SmallVector<Register, 8> PhysRegs;
-
OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
if (!determineAssignments(Assigner, OutArgs, CCInfo))
return false;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index a2b7cd088093a..98a3a981ed52b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -957,8 +957,6 @@ class MFMAExpInterleaveOpt final : public IGLPStrategy {
auto *DAG = SyncPipe[0].DAG;
if (Cache->empty()) {
- SmallVector<SUnit *, 8> Worklist;
-
auto I = DAG->SUnits.begin();
auto E = DAG->SUnits.end();
for (; I != E; I++) {
@@ -1290,7 +1288,6 @@ class MFMAExpInterleaveOpt final : public IGLPStrategy {
bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
- SmallVector<SUnit *, 12> Worklist;
auto *DAG = SyncPipe[0].DAG;
if (Cache->empty()) {
for (auto &SU : DAG->SUnits)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 1d0e81db5a5db..8822ae29e063e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1135,7 +1135,6 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(
if (LoadSize <= MaxNonSmrdLoadSize)
return false;
- SmallVector<Register, 16> DefRegs(OpdMapper.getVRegs(0));
SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1));
if (SrcRegs.empty())
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index aa025c5307226..9c2811006bc1c 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -1463,7 +1463,6 @@ SDValue R600TargetLowering::LowerFormalArguments(
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext());
MachineFunction &MF = DAG.getMachineFunction();
- SmallVector<ISD::InputArg, 8> LocalIns;
if (AMDGPU::isShader(CallConv)) {
CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index f1cbc26dcadf0..97ad0c2ce5158 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1629,7 +1629,6 @@ bool SIFoldOperandsImpl::foldCopyToAGPRRegSequence(MachineInstr *CopyMI) const {
MachineInstrBuilder B(*MBB.getParent(), CopyMI);
DenseMap<TargetInstrInfo::RegSubRegPair, Register> VGPRCopies;
- SmallSetVector<TargetInstrInfo::RegSubRegPair, 32> SeenInputs;
const TargetRegisterClass *UseRC =
MRI->getRegClass(CopyMI->getOperand(1).getReg());
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index c0c1831957719..ccdc3223ea983 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3235,7 +3235,6 @@ SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
// CCValAssign - represent the assignment of the return value to a location.
SmallVector<CCValAssign, 48> RVLocs;
- SmallVector<ISD::OutputArg, 48> Splits;
// CCState - Info about the registers and stack slots.
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 64c067f2b0993..b4598f26a8d9f 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -1891,7 +1891,6 @@ void ARMFrameLowering::emitFPStatusRestores(
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
- SmallVector<MCRegister> Regs;
auto RegPresent = [&CSI](MCRegister Reg) {
return llvm::any_of(CSI, [Reg](const CalleeSavedInfo &C) {
return C.getReg() == Reg;
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index c3cb700b21c68..dae08387cf8eb 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -2436,7 +2436,6 @@ static bool canTailPredicateLoop(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
// Next, check that all instructions can be tail-predicated.
PredicatedScalarEvolution PSE = LAI->getPSE();
- SmallVector<Instruction *, 16> LoadStores;
int ICmpCount = 0;
for (BasicBlock *BB : L->blocks()) {
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index 67ac69214be50..686e1609c376d 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -1348,7 +1348,6 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
MCContext &Context = getParser().getContext();
const MCRegisterInfo *RI = getContext().getRegisterInfo();
const std::string r = "r";
- const std::string v = "v";
const std::string Colon = ":";
using RegPairVals = std::pair<unsigned, unsigned>;
auto GetRegPair = [this, r](RegPairVals RegPair) {
diff --git a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
index 241db3fd5438a..fa8ae60e3f57b 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
@@ -519,7 +519,6 @@ void HexagonVectorLoopCarriedReuse::reuseValue() {
SmallVector<Instruction *, 4> InstsInPreheader;
for (int i = 0; i < Iterations; ++i) {
Instruction *InstInPreheader = Inst2Replace->clone();
- SmallVector<Value *, 4> Ops;
for (int j = 0; j < NumOperands; ++j) {
Instruction *I = dyn_cast<Instruction>(Inst2Replace->getOperand(j));
if (!I)
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 01c9d0b38323e..555773adf52aa 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -334,7 +334,6 @@ bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
splitToValueTypes(ArgRetInfo, RetInfos, DL, F.getCallingConv());
SmallVector<CCValAssign, 16> ArgLocs;
- SmallVector<ISD::OutputArg, 8> Outs;
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
F.getContext());
@@ -383,8 +382,6 @@ bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
++i;
}
- SmallVector<ISD::InputArg, 8> Ins;
-
SmallVector<CCValAssign, 16> ArgLocs;
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
F.getContext());
@@ -554,7 +551,6 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
F.getCallingConv());
const std::string FuncName = F.getName().str();
- SmallVector<ISD::InputArg, 8> Ins;
SmallVector<CCValAssign, 8> ArgLocs;
MipsIncomingValueAssigner Assigner(TLI.CCAssignFnForReturn(),
FuncName.c_str(),
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index e451f535809c2..67560072d311d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -552,7 +552,6 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
if (!FLI.CanLowerReturn)
insertSRetIncomingArgument(F, SplitArgInfos, FLI.DemoteRegister, MRI, DL);
- SmallVector<Type *, 4> TypeList;
unsigned Index = 0;
for (auto &Arg : F.args()) {
// Construct the ArgInfo object from destination register and argument type.
@@ -608,7 +607,6 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MIRBuilder.buildInstr(RISCV::ADJCALLSTACKDOWN);
SmallVector<ArgInfo, 32> SplitArgInfos;
- SmallVector<ISD::OutputArg, 8> Outs;
for (auto &AInfo : Info.OrigArgs) {
// Handle any required unmerging of split value types from a given VReg into
// physical registers. ArgInfo objects are constructed correspondingly and
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
index ea410015a82f3..656d5dd327739 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
@@ -1707,7 +1707,6 @@ void WebAssemblyLowerEmscriptenEHSjLj::handleLongjmpableCallsForWasmSjLj(
// BB. If the call is enclosed in another catchpad/cleanuppad scope, unwind
// to its parent pad's unwind destination instead to preserve the scope
// structure. It will eventually unwind to the catch.dispatch.longjmp.
- SmallVector<OperandBundleDef, 1> Bundles;
BasicBlock *UnwindDest = nullptr;
if (auto Bundle = CI->getOperandBundle(LLVMContext::OB_funclet)) {
Instruction *FromPad = cast<Instruction>(Bundle->Inputs[0]);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 483aceb239b0c..3d9c76f3d05f5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -21121,7 +21121,6 @@ static SDValue LowerTruncateVecPackWithSignBits(
// If the upper half of the source is undef, then attempt to split and
// only truncate the lower half.
if (DstVT.getSizeInBits() >= 128) {
- SmallVector<SDValue> LowerOps;
if (SDValue Lo = isUpperSubvectorUndef(In, DL, DAG)) {
MVT DstHalfVT = DstVT.getHalfNumVectorElementsVT();
if (SDValue Res = LowerTruncateVecPackWithSignBits(DstHalfVT, Lo, DL,
@@ -21164,7 +21163,6 @@ static SDValue LowerTruncateVecPack(MVT DstVT, SDValue In, const SDLoc &DL,
// If the upper half of the source is undef, then attempt to split and
// only truncate the lower half.
if (DstVT.getSizeInBits() >= 128) {
- SmallVector<SDValue> LowerOps;
if (SDValue Lo = isUpperSubvectorUndef(In, DL, DAG)) {
MVT DstHalfVT = DstVT.getHalfNumVectorElementsVT();
if (SDValue Res = LowerTruncateVecPack(DstHalfVT, Lo, DL, Subtarget, DAG))
diff --git a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
index fecfc3fa68469..cf055cf3be0aa 100644
--- a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
@@ -414,7 +414,6 @@ X86LoadValueInjectionLoadHardeningPass::getGadgetGraph(
// Check whether the use propagates to more defs.
NodeAddr<InstrNode *> Owner{Use.Addr->getOwner(DFG)};
- rdf::NodeList AnalyzedChildDefs;
for (const auto &ChildDef :
Owner.Addr->members_if(DataFlowGraph::IsDef, DFG)) {
if (!DefsVisited.insert(ChildDef.Id).second)
diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp
index 77253835b0590..278ae46b8a5f5 100644
--- a/llvm/lib/Target/X86/X86LowerAMXType.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp
@@ -1198,7 +1198,6 @@ bool X86LowerAMXCast::combineLdSt(SmallVectorImpl<Instruction *> &Casts) {
for (auto *Store : DeadStores)
Store->eraseFromParent();
} else { // x86_cast_vector_to_tile
- SmallVector<Instruction *, 2> DeadLoads;
auto *Load = dyn_cast<LoadInst>(Cast->getOperand(0));
if (!Load || !Load->hasOneUse())
continue;
``````````
</details>
https://github.com/llvm/llvm-project/pull/138443
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