[llvm] a9699a3 - [CodeGen] Use range-based for loops (NFC) (#138434)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 4 00:26:22 PDT 2025
Author: Kazu Hirata
Date: 2025-05-04T00:26:19-07:00
New Revision: a9699a334bc9666570418a3bed9520bcdc21518b
URL: https://github.com/llvm/llvm-project/commit/a9699a334bc9666570418a3bed9520bcdc21518b
DIFF: https://github.com/llvm/llvm-project/commit/a9699a334bc9666570418a3bed9520bcdc21518b.diff
LOG: [CodeGen] Use range-based for loops (NFC) (#138434)
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
llvm/lib/CodeGen/MachineCSE.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 908524313030f..a3d973f98e993 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1114,8 +1114,8 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
MaskTy = LLT::scalar(PtrTy.getSizeInBits());
else {
// Ensure that the type will fit the mask value.
- for (unsigned I = 0, E = B.Cases.size(); I != E; ++I) {
- if (!isUIntN(SwitchOpTy.getSizeInBits(), B.Cases[I].Mask)) {
+ for (const SwitchCG::BitTestCase &Case : B.Cases) {
+ if (!isUIntN(SwitchOpTy.getSizeInBits(), Case.Mask)) {
// Switch table case range are encoded into series of masks.
// Just use pointer type, it's guaranteed to fit.
MaskTy = LLT::scalar(PtrTy.getSizeInBits());
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 4052060271331..57db09ca9d099 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -5500,9 +5500,8 @@ LegalizerHelper::fewerElementsBitcast(MachineInstr &MI, unsigned int TypeIdx,
// Build new smaller bitcast instructions
// Not supporting Leftover types for now but will have to
- for (unsigned i = 0; i < SrcVRegs.size(); i++)
- BitcastVRegs.push_back(
- MIRBuilder.buildBitcast(NarrowTy, SrcVRegs[i]).getReg(0));
+ for (Register Reg : SrcVRegs)
+ BitcastVRegs.push_back(MIRBuilder.buildBitcast(NarrowTy, Reg).getReg(0));
MIRBuilder.buildMergeLikeInstr(DstReg, BitcastVRegs);
MI.eraseFromParent();
@@ -7383,9 +7382,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerTRUNC(MachineInstr &MI) {
InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits() * 2);
else
InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits());
- for (unsigned I = 0; I < SplitSrcs.size(); ++I) {
- SplitSrcs[I] = MIRBuilder.buildTrunc(InterTy, SplitSrcs[I]).getReg(0);
- }
+ for (Register &Src : SplitSrcs)
+ Src = MIRBuilder.buildTrunc(InterTy, Src).getReg(0);
// Combine the new truncates into one vector
auto Merge = MIRBuilder.buildMergeLikeInstr(
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 6bbd130fa7a9e..5d6e7f1e67a4e 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -2588,8 +2588,7 @@ void InstrRefBasedLDV::placeMLocPHIs(
auto CollectPHIsForLoc = [&](LocIdx L) {
// Collect the set of defs.
SmallPtrSet<MachineBasicBlock *, 32> DefBlocks;
- for (unsigned int I = 0; I < OrderToBB.size(); ++I) {
- MachineBasicBlock *MBB = OrderToBB[I];
+ for (MachineBasicBlock *MBB : OrderToBB) {
const auto &TransferFunc = MLocTransfer[MBB->getNumber()];
if (TransferFunc.contains(L))
DefBlocks.insert(MBB);
@@ -3800,8 +3799,7 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF,
// To mirror old LiveDebugValues, enumerate variables in RPOT order. Otherwise
// the order is unimportant, it just has to be stable.
unsigned VarAssignCount = 0;
- for (unsigned int I = 0; I < OrderToBB.size(); ++I) {
- auto *MBB = OrderToBB[I];
+ for (MachineBasicBlock *MBB : OrderToBB) {
auto *VTracker = &vlocs[MBB->getNumber()];
// Collect each variable with a DBG_VALUE in this block.
for (auto &idx : VTracker->Vars) {
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 6d14509c5934f..bebdead5ecb89 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -325,9 +325,8 @@ bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
}
// Finally, add all defs to PhysRefs as well.
- for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
- for (MCRegAliasIterator AI(PhysDefs[i].second, TRI, true); AI.isValid();
- ++AI)
+ for (const auto &Def : PhysDefs)
+ for (MCRegAliasIterator AI(Def.second, TRI, true); AI.isValid(); ++AI)
PhysRefs.insert(*AI);
return !PhysRefs.empty();
@@ -348,9 +347,8 @@ bool MachineCSEImpl::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
return false;
- for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
- if (MRI->isAllocatable(PhysDefs[i].second) ||
- MRI->isReserved(PhysDefs[i].second))
+ for (const auto &PhysDef : PhysDefs) {
+ if (MRI->isAllocatable(PhysDef.second) || MRI->isReserved(PhysDef.second))
// Avoid extending live range of physical registers if they are
//allocatable or reserved.
return false;
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index 83a9c0d738394..39d0f8613a400 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -321,12 +321,11 @@ void RenameIndependentSubregs::computeMainRangesFixFlags(
// Search for "PHI" value numbers in the subranges. We must find a live
// value in each predecessor block, add an IMPLICIT_DEF where it is
// missing.
- for (unsigned I = 0; I < SR.valnos.size(); ++I) {
- const VNInfo &VNI = *SR.valnos[I];
- if (VNI.isUnused() || !VNI.isPHIDef())
+ for (const VNInfo *VNI : SR.valnos) {
+ if (VNI->isUnused() || !VNI->isPHIDef())
continue;
- SlotIndex Def = VNI.def;
+ SlotIndex Def = VNI->def;
MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(Def);
for (MachineBasicBlock *PredMBB : MBB.predecessors()) {
SlotIndex PredEnd = Indexes.getMBBEndIdx(PredMBB);
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 30f65bde142d2..a521a82e24d6b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -360,8 +360,8 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
DelDeps.push_back(std::make_pair(SuccSU, D));
}
}
- for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
- RemovePred(DelDeps[i].first, DelDeps[i].second);
+ for (const auto &Dep : DelDeps)
+ RemovePred(Dep.first, Dep.second);
++NumDups;
return NewSU;
@@ -395,8 +395,8 @@ void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
DelDeps.push_back(std::make_pair(SuccSU, Succ));
}
}
- for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
- RemovePred(DelDeps[i].first, DelDeps[i].second);
+ for (const auto &Dep : DelDeps) {
+ RemovePred(Dep.first, Dep.second);
}
SDep FromDep(SU, SDep::Data, Reg);
FromDep.setLatency(SU->Latency);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 881b1536a131f..7030f0a926a33 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3161,8 +3161,8 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
if (!TLI.isTypeLegal(VT)) {
UsePtrType = true;
} else {
- for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
- if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
+ for (const BitTestCase &Case : B.Cases)
+ if (!isUIntN(VT.getSizeInBits(), Case.Mask)) {
// Switch table case range are encoded into series of masks.
// Just use pointer type, it's guaranteed to fit.
UsePtrType = true;
More information about the llvm-commits
mailing list