[llvm] 56433e8 - [SPARC][IAS][NFC] Tidy up LDSTUB and 64-bit mul/div instruction definitions

[via llvm-commits]

Author: Koakuma
Date: 2025-05-04T09:38:02+07:00
New Revision: 56433e874b96bf7b3da02c13226a996d4fa5aef8

URL: https://github.com/llvm/llvm-project/commit/56433e874b96bf7b3da02c13226a996d4fa5aef8
DIFF: https://github.com/llvm/llvm-project/commit/56433e874b96bf7b3da02c13226a996d4fa5aef8.diff

LOG: [SPARC][IAS][NFC] Tidy up LDSTUB and 64-bit mul/div instruction definitions



Reviewers: brad0, rorth, s-barannikov

Reviewed By: s-barannikov

Pull Request: https://github.com/llvm/llvm-project/pull/138398

Added: 
    

Modified: 
    llvm/lib/Target/Sparc/SparcInstr64Bit.td
    llvm/lib/Target/Sparc/SparcInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index 372ab80a3bb71..5dc19144bebe9 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
 //===----------------------------------------------------------------------===//
 
 let Predicates = [Is64Bit] in {
-
-def MULXrr : F3_1<2, 0b001001,
-                  (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
-                  "mulx $rs1, $rs2, $rd",
-                  [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
-def MULXri : F3_2<2, 0b001001,
-                  (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
-                  "mulx $rs1, $simm13, $rd",
-                  [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
+defm MULX    : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>;
 
 // Division can trap.
 let hasSideEffects = 1 in {
-def SDIVXrr : F3_1<2, 0b101101,
-                   (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
-                   "sdivx $rs1, $rs2, $rd",
-                   [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
-def SDIVXri : F3_2<2, 0b101101,
-                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
-                   "sdivx $rs1, $simm13, $rd",
-                   [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
-
-def UDIVXrr : F3_1<2, 0b001101,
-                   (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
-                   "udivx $rs1, $rs2, $rd",
-                   [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
-def UDIVXri : F3_2<2, 0b001101,
-                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
-                   "udivx $rs1, $simm13, $rd",
-                   [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
+defm SDIVX    : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>;
+defm UDIVX    : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>;
 } // hasSideEffects = 1
-
 } // Predicates = [Is64Bit]
 
 

diff  --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 02f4b202e9645..0c890721da0f4 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -467,22 +467,6 @@ multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
   defm A   : LoadASI<OpcStr, LoadAOp3Val, RC>;
 }
 
-
-// The LDSTUB instruction is supported for asm only.
-// It is unlikely that general-purpose code could make use of it.
-// CAS is preferred for sparc v9.
-def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
-                    "ldstub [$addr], $rd", []>;
-def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
-                    "ldstub [$addr], $rd", []>;
-def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
-                         (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
-                         "ldstuba [$addr] $asi, $rd", []>;
-let Predicates = [HasV9], Uses = [ASR3] in
-def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
-                         (ins (MEMri $rs1, $simm13):$addr),
-                         "ldstuba [$addr] %asi, $rd", []>;
-
 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
            RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
@@ -740,6 +724,22 @@ let rd = 1, mayStore = 1, Uses = [FSR] in {
 		 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
 }
 
+// B.7. Atomic Load-Store Unsigned Byte Instructions
+// (Atomic test-and-set)
+// TODO look into the possibility to use this to implment `atomic_flag`.
+// If it's possible, then LDSTUB is the preferred way to do it.
+def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
+                    "ldstub [$addr], $rd", []>;
+def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
+                    "ldstub [$addr], $rd", []>;
+def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
+                         (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
+                         "ldstuba [$addr] $asi, $rd", []>;
+let Predicates = [HasV9], Uses = [ASR3] in
+def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
+                         (ins (MEMri $rs1, $simm13):$addr),
+                         "ldstuba [$addr] %asi, $rd", []>;
+
 // Section B.8 - SWAP Register with Memory Instruction
 // (Atomic swap)
 let Constraints = "$val = $rd" in {