[llvm] [AArch64][SelectionDAG] Add support for 8to64 partial reduction cases (PR #138269)

[Sander de Smalen via llvm-commits]

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@@ -29509,6 +29514,41 @@ SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
   return Scatter;
 }
 
+/// If a PARTIAL_REDUCE_MLA node comes in with an accumulator type that is too
+/// wide to be used for (u|s)dot, we can still make use of the dot product
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sdesmalen-arm wrote:

nit: rather than speaking of 'types that are too wide', I'd suggest being explicit about the types, e.g. we can't accumulate from nxv16i8 -> nxv2i64 in one step, but we can accumulate in two steps: nxv16i8 -> nxv4i32 ->  nxv2i64.

https://github.com/llvm/llvm-project/pull/138269