[llvm] [AArch64] Implement assembler support for new SVE SEH unwind opcodes. (PR #137895)

[Pedro Miguel Justo via llvm-commits]

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@@ -640,6 +645,37 @@ static void ARM64EmitUnwindCode(MCStreamer &streamer,
     streamer.emitInt8(b);
     break;
   }
+  case Win64EH::UOP_AllocZ: {
+    b = 0xDF;
+    streamer.emitInt8(b);
+    b = inst.Offset;
+    streamer.emitInt8(b);
+    break;
+  }
+  case Win64EH::UOP_SaveZReg: {
+    assert(inst.Register >= 8 && inst.Register <= 23);
+    assert(inst.Offset < 256);
+    b = 0xE7;
+    streamer.emitInt8(b);
+    reg = inst.Register - 8;
+    b = ((inst.Offset & 0xC0) >> 1) | reg;
+    streamer.emitInt8(b);
+    b = 0xC0 | (inst.Offset & 0x3F);
+    streamer.emitInt8(b);
+    break;
+  }
+  case Win64EH::UOP_SavePReg: {
+    assert(inst.Register >= 4 && inst.Register <= 15);
+    assert(inst.Offset < 256);
+    b = 0xE7;
+    streamer.emitInt8(b);
+    reg = inst.Register - 4;
----------------
pmsjt wrote:

> The docs seem to be inconsistent here - the docs say `save reg P(#r+8) at [sp + #o * (VL / 8)], (P4 through P15; r values [0, 3] are reserved)`. I presume that it should be `P(#r+4)` which would match this code, which would make sense. But the comment about which values are reserved makes me wonder if it is `P(#r)`, so it covers the range P0-P15, but P0-P3 shouldn't be touched here?

Good catch. that +8 is bogus. Should be 

`save reg P(#r) at [sp + #o * (VL / 8)], (P4 through P15; r values [0, 3] are reserved)`

I'll push a doc update ASAP.



https://github.com/llvm/llvm-project/pull/137895