[llvm] [AArch64][SelectionDAG] Add support for 8to64 partial reduction cases (PR #138269)

[Nicholas Guy via llvm-commits]

================
@@ -29509,6 +29514,28 @@ SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
   return Scatter;
 }
 
+SDValue
+AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+
+  auto Acc = Op.getOperand(0);
+  auto LHS = Op.getOperand(1);
+  auto RHS = Op.getOperand(2);
+  auto ResultVT = Op.getValueType();
+  assert(ResultVT == MVT::nxv2i64 && LHS.getValueType() == MVT::nxv16i8);
+
+  EVT InputVT = MVT::nxv4i32;
+  SDValue DotNode = DAG.getNode(Op.getOpcode(), DL, InputVT,
+                                DAG.getConstant(0, DL, InputVT), LHS, RHS);
+
+  bool IsUnsigned = Op.getOpcode() == ISD::PARTIAL_REDUCE_UMLA;
+  unsigned LoOpcode = IsUnsigned ? AArch64ISD::UADDWB : AArch64ISD::SADDWB;
+  unsigned HiOpcode = IsUnsigned ? AArch64ISD::UADDWT : AArch64ISD::SADDWT;
----------------
NickGuy-Arm wrote:

I had that at first, but removed it as the PartialReduceMLAAction was only set if we had SVE, not realising that these instructions were specifically SVE**2**. Added, as well as a fallback to the old unpack/add approach for when we don't have SVE2.

https://github.com/llvm/llvm-project/pull/138269