[llvm] [AArch64][SelectionDAG] Add support for 8to64 partial reduction cases (PR #138269)

[Sander de Smalen via llvm-commits]

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@@ -29509,6 +29514,28 @@ SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
   return Scatter;
 }
 
+SDValue
+AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
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sdesmalen-arm wrote:

Can you add a comment describing what this code is doing?

https://github.com/llvm/llvm-project/pull/138269