[llvm] [DAGCombiner] Fold pattern for srl-shl-zext (PR #138290)

[Simon Pilgrim via llvm-commits]

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@@ -10979,6 +10979,39 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
       return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
   }
 
+  // fold (srl (or x, (shl (zext y), c1)), c1) -> (or (srl x, c1), (zext y))
+  // c1 <= leadingzeros(zext(y))
+  if (N1C && (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND ||
+              N0.getOpcode() == ISD::XOR)) {
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RKSimon wrote:

`N1C && ISD::isBitwiseLogicOp(N0.getOpcode()))`

(ideally we'd use sd_match but we're missing m_BitwiseLogic)

https://github.com/llvm/llvm-project/pull/138290