[llvm] [AArch64][SelectionDAG] Add support for 8to64 partial reduction cases (PR #138269)

[Benjamin Maxwell via llvm-commits]

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@@ -29509,6 +29514,29 @@ SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
   return Scatter;
 }
 
+SDValue
+AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+
+  auto Acc = Op.getOperand(0);
+  auto LHS = Op.getOperand(1);
+  auto RHS = Op.getOperand(2);
+
+  auto ResultVT = Op.getValueType();
+
+  assert(ResultVT == MVT::nxv2i64 && LHS.getValueType() == MVT::nxv16i8);
+
+  auto NewAcc = DAG.getConstant(0, DL, MVT::nxv4i32);
+  auto DotNode =
+      DAG.getNode(Op.getOpcode(), DL, MVT::nxv4i32, NewAcc, LHS, RHS);
+
+  auto Lo = DAG.getNode(AArch64ISD::UUNPKLO, DL, ResultVT, DotNode);
+  auto Hi = DAG.getNode(AArch64ISD::UUNPKHI, DL, ResultVT, DotNode);
+  auto Extended = DAG.getNode(ISD::ADD, DL, ResultVT, Lo, Hi);
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MacDue wrote:

Also, is `UUNPKLO/HI` correct for `sdot`? IIRC it only zero extends. 

https://github.com/llvm/llvm-project/pull/138269