[llvm] [WIP][CodeGen] Modifying MBB's liveins representation as into regUnits (PR #129847)
Vikash Gupta via llvm-commits
llvm-commits at lists.llvm.org
Fri May 2 00:38:19 PDT 2025
https://github.com/vg0204 updated https://github.com/llvm/llvm-project/pull/129847
>From aa1a255b37b3277f79423d3d71baa0b771e27ef0 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Wed, 5 Mar 2025 06:20:45 +0000
Subject: [PATCH 1/3] [CodeGen] Utilizing register units based liveIns tracking
Currently, the machine basicblock does not fully utilizes the
laneBitmask associated with physReg liveIns to check for the
precise liveness. Conservatively, it acts fully correct now, only
if all liveIns check for MBB is in form it defines it for itself.
So, now with the use of register units tracking for MBB's liveIns
, its possible to track & check liveness for all sorts of physRegs.
---
llvm/include/llvm/CodeGen/MachineBasicBlock.h | 15 ++++++++
llvm/lib/CodeGen/MachineBasicBlock.cpp | 34 ++++++++++++++++---
llvm/test/CodeGen/ARM/aes-erratum-fix.ll | 8 ++---
3 files changed, 48 insertions(+), 9 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index 2de96fa85b936..ab88177b63fed 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -13,6 +13,7 @@
#ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMapInfo.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/SparseBitVector.h"
@@ -158,6 +159,7 @@ class MachineBasicBlock
MachineFunction *xParent;
Instructions Insts;
+ const TargetRegisterInfo *TRI;
/// Keep track of the predecessor / successor basic blocks.
SmallVector<MachineBasicBlock *, 4> Predecessors;
@@ -177,6 +179,10 @@ class MachineBasicBlock
using LiveInVector = std::vector<RegisterMaskPair>;
LiveInVector LiveIns;
+ /// Keeps track of live register units for those physical registers which
+ /// are livein of the basicblock.
+ BitVector LiveInRegUnits;
+
/// Alignment of the basic block. One if the basic block does not need to be
/// aligned.
Align Alignment;
@@ -458,11 +464,17 @@ class MachineBasicBlock
void addLiveIn(MCRegister PhysReg,
LaneBitmask LaneMask = LaneBitmask::getAll()) {
LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
+ addLiveInRegUnit(PhysReg, LaneMask);
}
void addLiveIn(const RegisterMaskPair &RegMaskPair) {
LiveIns.push_back(RegMaskPair);
+ addLiveInRegUnit(RegMaskPair.PhysReg, RegMaskPair.LaneMask);
}
+ // Sets the register units for Reg based on the LaneMask in the
+ // LiveInRegUnits.
+ void addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask);
+
/// Sorts and uniques the LiveIns vector. It can be significantly faster to do
/// this than repeatedly calling isLiveIn before calling addLiveIn for every
/// LiveIn insertion.
@@ -484,6 +496,9 @@ class MachineBasicBlock
void removeLiveIn(MCRegister Reg,
LaneBitmask LaneMask = LaneBitmask::getAll());
+ /// Resets the register units from LiveInRegUnits for the specified regsiters.
+ void removeLiveInRegUnit(MCRegister Reg);
+
/// Return true if the specified register is in the live in set.
bool isLiveIn(MCRegister Reg,
LaneBitmask LaneMask = LaneBitmask::getAll()) const;
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index b3a71d1144726..0e5055d7bec2c 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -35,6 +35,7 @@
#include "llvm/IR/ModuleSlotTracker.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
@@ -51,10 +52,12 @@ static cl::opt<bool> PrintSlotIndexes(
cl::init(true), cl::Hidden);
MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
- : BB(B), Number(-1), xParent(&MF) {
+ : BB(B), Number(-1), xParent(&MF),
+ TRI(MF.getSubtarget().getRegisterInfo()) {
Insts.Parent = this;
if (B)
IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight();
+ LiveInRegUnits.resize(TRI->getNumRegUnits());
}
MachineBasicBlock::~MachineBasicBlock() = default;
@@ -597,6 +600,14 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
printName(OS, 0);
}
+void MachineBasicBlock::addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask) {
+ for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
+ LaneBitmask UnitMask = (*Unit).second;
+ if ((UnitMask & LaneMask).any())
+ LiveInRegUnits.set((*Unit).first);
+ }
+}
+
void MachineBasicBlock::removeLiveIn(MCRegister Reg, LaneBitmask LaneMask) {
LiveInVector::iterator I = find_if(
LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
@@ -604,21 +615,32 @@ void MachineBasicBlock::removeLiveIn(MCRegister Reg, LaneBitmask LaneMask) {
return;
I->LaneMask &= ~LaneMask;
- if (I->LaneMask.none())
+ if (I->LaneMask.none()) {
LiveIns.erase(I);
+ removeLiveInRegUnit(I->PhysReg);
+ }
}
MachineBasicBlock::livein_iterator
MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
// Get non-const version of iterator.
LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin());
+ removeLiveInRegUnit(LI->PhysReg);
return LiveIns.erase(LI);
}
+void MachineBasicBlock::removeLiveInRegUnit(MCRegister Reg) {
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ LiveInRegUnits.reset(Unit);
+}
+
bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
- livein_iterator I = find_if(
- LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
- return I != livein_end() && (I->LaneMask & LaneMask).any();
+ for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
+ LaneBitmask UnitMask = (*Unit).second;
+ if ((UnitMask & LaneMask).any() && LiveInRegUnits.test((*Unit).first))
+ return true;
+ }
+ return false;
}
void MachineBasicBlock::sortUniqueLiveIns() {
@@ -1751,12 +1773,14 @@ MachineBasicBlock::getEndClobberMask(const TargetRegisterInfo *TRI) const {
void MachineBasicBlock::clearLiveIns() {
LiveIns.clear();
+ LiveInRegUnits.reset();
}
void MachineBasicBlock::clearLiveIns(
std::vector<RegisterMaskPair> &OldLiveIns) {
assert(OldLiveIns.empty() && "Vector must be empty");
std::swap(LiveIns, OldLiveIns);
+ LiveInRegUnits.reset();
}
MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const {
diff --git a/llvm/test/CodeGen/ARM/aes-erratum-fix.ll b/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
index 82f5bfd02a56e..e1361d6efa780 100644
--- a/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
+++ b/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
@@ -68,8 +68,8 @@ define arm_aapcs_vfpcc void @aese_via_call2(half %0, ptr %1) nounwind {
; CHECK-FIX-NEXT: push {r4, lr}
; CHECK-FIX-NEXT: mov r4, r0
; CHECK-FIX-NEXT: bl get_inputf16
-; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
+; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: aese.8 q8, q0
; CHECK-FIX-NEXT: aesmc.8 q8, q8
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]
@@ -89,8 +89,8 @@ define arm_aapcs_vfpcc void @aese_via_call3(float %0, ptr %1) nounwind {
; CHECK-FIX-NEXT: push {r4, lr}
; CHECK-FIX-NEXT: mov r4, r0
; CHECK-FIX-NEXT: bl get_inputf32
-; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
+; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: aese.8 q8, q0
; CHECK-FIX-NEXT: aesmc.8 q8, q8
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]
@@ -2222,8 +2222,8 @@ define arm_aapcs_vfpcc void @aesd_via_call2(half %0, ptr %1) nounwind {
; CHECK-FIX-NEXT: push {r4, lr}
; CHECK-FIX-NEXT: mov r4, r0
; CHECK-FIX-NEXT: bl get_inputf16
-; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
+; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: aesd.8 q8, q0
; CHECK-FIX-NEXT: aesimc.8 q8, q8
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]
@@ -2243,8 +2243,8 @@ define arm_aapcs_vfpcc void @aesd_via_call3(float %0, ptr %1) nounwind {
; CHECK-FIX-NEXT: push {r4, lr}
; CHECK-FIX-NEXT: mov r4, r0
; CHECK-FIX-NEXT: bl get_inputf32
-; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4]
+; CHECK-FIX-NEXT: vorr q0, q0, q0
; CHECK-FIX-NEXT: aesd.8 q8, q0
; CHECK-FIX-NEXT: aesimc.8 q8, q8
; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4]
>From 0b4c961320e274d37997bc699e66bf3ddaf42a57 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Mon, 10 Mar 2025 10:21:46 +0000
Subject: [PATCH 2/3] Removed the TRI as member function of machine basicblock.
---
llvm/include/llvm/CodeGen/MachineBasicBlock.h | 1 -
llvm/lib/CodeGen/MachineBasicBlock.cpp | 8 +++++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index ab88177b63fed..e93ffcbe34124 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -159,7 +159,6 @@ class MachineBasicBlock
MachineFunction *xParent;
Instructions Insts;
- const TargetRegisterInfo *TRI;
/// Keep track of the predecessor / successor basic blocks.
SmallVector<MachineBasicBlock *, 4> Predecessors;
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 0e5055d7bec2c..417ef3c028b25 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -52,12 +52,11 @@ static cl::opt<bool> PrintSlotIndexes(
cl::init(true), cl::Hidden);
MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
- : BB(B), Number(-1), xParent(&MF),
- TRI(MF.getSubtarget().getRegisterInfo()) {
+ : BB(B), Number(-1), xParent(&MF) {
Insts.Parent = this;
if (B)
IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight();
- LiveInRegUnits.resize(TRI->getNumRegUnits());
+ LiveInRegUnits.resize(MF.getSubtarget().getRegisterInfo()->getNumRegUnits());
}
MachineBasicBlock::~MachineBasicBlock() = default;
@@ -601,6 +600,7 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
}
void MachineBasicBlock::addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask) {
+ const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
LaneBitmask UnitMask = (*Unit).second;
if ((UnitMask & LaneMask).any())
@@ -630,11 +630,13 @@ MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
}
void MachineBasicBlock::removeLiveInRegUnit(MCRegister Reg) {
+ const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
for (MCRegUnit Unit : TRI->regunits(Reg))
LiveInRegUnits.reset(Unit);
}
bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
+ const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
LaneBitmask UnitMask = (*Unit).second;
if ((UnitMask & LaneMask).any() && LiveInRegUnits.test((*Unit).first))
>From 931ae3c8067429f91f568bee5a057091c7a1b1d7 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Fri, 2 May 2025 06:35:40 +0000
Subject: [PATCH 3/3] Updated the MBB-liveins to track liveRegUnits's Root
registers and their respective use-sites
---
llvm/include/llvm/CodeGen/LivePhysRegs.h | 6 +-
llvm/include/llvm/CodeGen/MachineBasicBlock.h | 54 +++------
llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 2 +-
llvm/lib/CodeGen/BranchFolding.cpp | 7 +-
llvm/lib/CodeGen/BranchRelaxation.cpp | 3 +-
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp | 2 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 3 +-
llvm/lib/CodeGen/LiveIntervals.cpp | 2 +-
llvm/lib/CodeGen/LivePhysRegs.cpp | 17 +--
llvm/lib/CodeGen/LiveRegUnits.cpp | 2 +-
llvm/lib/CodeGen/LiveVariables.cpp | 9 +-
llvm/lib/CodeGen/MIRPrinter.cpp | 6 +-
llvm/lib/CodeGen/MachineBasicBlock.cpp | 105 +++++++-----------
llvm/lib/CodeGen/MachineCopyPropagation.cpp | 2 +-
llvm/lib/CodeGen/MachineLICM.cpp | 2 +-
llvm/lib/CodeGen/MachineSink.cpp | 1 -
llvm/lib/CodeGen/MachineVerifier.cpp | 51 +++++----
llvm/lib/CodeGen/PrologEpilogInserter.cpp | 4 +-
llvm/lib/CodeGen/RDFGraph.cpp | 4 +-
llvm/lib/CodeGen/RDFLiveness.cpp | 24 ++--
llvm/lib/CodeGen/ReachingDefAnalysis.cpp | 2 +-
llvm/lib/CodeGen/RegAllocFast.cpp | 5 +-
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 7 +-
llvm/lib/CodeGen/ShrinkWrap.cpp | 4 +-
llvm/lib/CodeGen/VirtRegMap.cpp | 5 -
llvm/lib/Target/AArch64/AArch64CollectLOH.cpp | 2 +-
.../Target/AArch64/AArch64FrameLowering.cpp | 10 +-
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 4 -
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 1 -
.../Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 -
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 4 +-
llvm/lib/Target/ARM/ARMFrameLowering.cpp | 2 -
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 8 +-
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp | 2 +-
llvm/lib/Target/AVR/AVRFrameLowering.cpp | 2 +-
.../lib/Target/Hexagon/HexagonBlockRanges.cpp | 13 +--
.../Target/Hexagon/HexagonCFGOptimizer.cpp | 11 +-
llvm/lib/Target/M68k/M68kFrameLowering.cpp | 4 +-
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 4 +-
llvm/lib/Target/X86/X86FloatingPoint.cpp | 2 +-
llvm/lib/Target/X86/X86FrameLowering.cpp | 3 +-
.../llvm-exegesis/lib/SnippetRepetitor.cpp | 2 +-
.../X86/SnippetRepetitorTest.cpp | 15 +--
43 files changed, 155 insertions(+), 265 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LivePhysRegs.h b/llvm/include/llvm/CodeGen/LivePhysRegs.h
index 696e8a0c5dd59..b61d6b5846549 100644
--- a/llvm/include/llvm/CodeGen/LivePhysRegs.h
+++ b/llvm/include/llvm/CodeGen/LivePhysRegs.h
@@ -199,14 +199,12 @@ void computeAndAddLiveIns(LivePhysRegs &LiveRegs,
/// any changes were made.
static inline bool recomputeLiveIns(MachineBasicBlock &MBB) {
LivePhysRegs LPR;
- std::vector<MachineBasicBlock::RegisterMaskPair> OldLiveIns;
+ DenseSet<MCRegister> OldLiveIns;
MBB.clearLiveIns(OldLiveIns);
computeAndAddLiveIns(LPR, MBB);
- MBB.sortUniqueLiveIns();
- const std::vector<MachineBasicBlock::RegisterMaskPair> &NewLiveIns =
- MBB.getLiveIns();
+ const DenseSet<MCRegister> &NewLiveIns = MBB.getLiveIns();
return OldLiveIns != NewLiveIns;
}
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index e93ffcbe34124..0c69264d78ecd 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -15,6 +15,7 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMapInfo.h"
+#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/ADT/ilist.h"
@@ -175,12 +176,7 @@ class MachineBasicBlock
std::optional<uint64_t> IrrLoopHeaderWeight;
/// Keep track of the physical registers that are livein of the basicblock.
- using LiveInVector = std::vector<RegisterMaskPair>;
- LiveInVector LiveIns;
-
- /// Keeps track of live register units for those physical registers which
- /// are livein of the basicblock.
- BitVector LiveInRegUnits;
+ DenseSet<MCRegister> LiveIns;
/// Alignment of the basic block. One if the basic block does not need to be
/// aligned.
@@ -457,34 +453,17 @@ class MachineBasicBlock
// LiveIn management methods.
- /// Adds the specified register as a live in. Note that it is an error to add
- /// the same register to the same set more than once unless the intention is
- /// to call sortUniqueLiveIns after all registers are added.
+ /// Adds the live regUnits(both of its roots registers) as the live in, based
+ /// on the LaneMask.
void addLiveIn(MCRegister PhysReg,
- LaneBitmask LaneMask = LaneBitmask::getAll()) {
- LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
- addLiveInRegUnit(PhysReg, LaneMask);
- }
- void addLiveIn(const RegisterMaskPair &RegMaskPair) {
- LiveIns.push_back(RegMaskPair);
- addLiveInRegUnit(RegMaskPair.PhysReg, RegMaskPair.LaneMask);
- }
-
- // Sets the register units for Reg based on the LaneMask in the
- // LiveInRegUnits.
- void addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask);
-
- /// Sorts and uniques the LiveIns vector. It can be significantly faster to do
- /// this than repeatedly calling isLiveIn before calling addLiveIn for every
- /// LiveIn insertion.
- void sortUniqueLiveIns();
+ LaneBitmask LaneMask = LaneBitmask::getAll());
/// Clear live in list.
void clearLiveIns();
/// Clear the live in list, and return the removed live in's in \p OldLiveIns.
/// Requires that the vector \p OldLiveIns is empty.
- void clearLiveIns(std::vector<RegisterMaskPair> &OldLiveIns);
+ void clearLiveIns(DenseSet<MCRegister> &OldLiveIns);
/// Add PhysReg as live in to this block, and ensure that there is a copy of
/// PhysReg to a virtual register of class RC. Return the virtual register
@@ -495,16 +474,13 @@ class MachineBasicBlock
void removeLiveIn(MCRegister Reg,
LaneBitmask LaneMask = LaneBitmask::getAll());
- /// Resets the register units from LiveInRegUnits for the specified regsiters.
- void removeLiveInRegUnit(MCRegister Reg);
-
/// Return true if the specified register is in the live in set.
bool isLiveIn(MCRegister Reg,
LaneBitmask LaneMask = LaneBitmask::getAll()) const;
// Iteration support for live in sets. These sets are kept in sorted
// order by their register number.
- using livein_iterator = LiveInVector::const_iterator;
+ using livein_iterator = DenseSet<MCRegister>::const_iterator;
/// Unlike livein_begin, this method does not check that the liveness
/// information is accurate. Still for debug purposes it may be useful
@@ -525,15 +501,15 @@ class MachineBasicBlock
/// Remove entry from the livein set and return iterator to the next.
livein_iterator removeLiveIn(livein_iterator I);
- const std::vector<RegisterMaskPair> &getLiveIns() const { return LiveIns; }
+ const DenseSet<MCRegister> &getLiveIns() const { return LiveIns; }
class liveout_iterator {
public:
using iterator_category = std::input_iterator_tag;
using difference_type = std::ptrdiff_t;
- using value_type = RegisterMaskPair;
- using pointer = const RegisterMaskPair *;
- using reference = const RegisterMaskPair &;
+ using value_type = MCRegister;
+ using pointer = const MCRegister *;
+ using reference = const MCRegister &;
liveout_iterator(const MachineBasicBlock &MBB, MCPhysReg ExceptionPointer,
MCPhysReg ExceptionSelector, bool End)
@@ -546,8 +522,7 @@ class MachineBasicBlock
LiveRegI = (*BlockI)->livein_begin();
if (!advanceToValidPosition())
return;
- if (LiveRegI->PhysReg == ExceptionPointer ||
- LiveRegI->PhysReg == ExceptionSelector)
+ if (*LiveRegI == ExceptionPointer || *LiveRegI == ExceptionSelector)
++(*this);
}
}
@@ -557,9 +532,8 @@ class MachineBasicBlock
++LiveRegI;
if (!advanceToValidPosition())
return *this;
- } while ((*BlockI)->isEHPad() &&
- (LiveRegI->PhysReg == ExceptionPointer ||
- LiveRegI->PhysReg == ExceptionSelector));
+ } while ((*BlockI)->isEHPad() && (*LiveRegI == ExceptionPointer ||
+ *LiveRegI == ExceptionSelector));
return *this;
}
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index 73200e705f213..cd29584ce96dc 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -153,7 +153,7 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
// Examine the live-in regs of all successors.
for (MachineBasicBlock *Succ : BB->successors())
for (const auto &LI : Succ->liveins()) {
- for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
+ for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
unsigned Reg = *AI;
State->UnionGroups(Reg, 0);
KillIndices[Reg] = BB->size();
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index 5218e39b88222..b9edef5ac5fbe 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -376,12 +376,7 @@ void BranchFolder::replaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
// Merging the tails may have switched some undef operand to non-undef ones.
// Add IMPLICIT_DEFS into OldMBB as necessary to have a definition of the
// register.
- for (MachineBasicBlock::RegisterMaskPair P : NewDest.liveins()) {
- // We computed the liveins with computeLiveIn earlier and should only see
- // full registers:
- assert(P.LaneMask == LaneBitmask::getAll() &&
- "Can only handle full register.");
- MCRegister Reg = P.PhysReg;
+ for (MCRegister Reg : NewDest.liveins()) {
if (!LiveRegs.available(*MRI, Reg))
continue;
DebugLoc DL;
diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index a762aab43ddd2..89772c30b55e6 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -573,11 +573,10 @@ bool BranchRelaxation::fixupUnconditionalBranch(MachineInstr &MI) {
// Add live outs.
for (const MachineBasicBlock *Succ : MBB->successors()) {
- for (const MachineBasicBlock::RegisterMaskPair &LiveIn : Succ->liveins())
+ for (const MCRegister LiveIn : Succ->liveins())
BranchBB->addLiveIn(LiveIn);
}
- BranchBB->sortUniqueLiveIns();
BranchBB->addSuccessor(DestBB);
MBB->replaceSuccessor(DestBB, BranchBB);
if (TrampolineInsertionPoint == MBB)
diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
index e4bf77b6563a5..2b6fe39358b8d 100644
--- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
@@ -66,7 +66,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
// Examine the live-in regs of all successors.
for (const MachineBasicBlock *Succ : BB->successors())
for (const auto &LI : Succ->liveins()) {
- for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
+ for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
unsigned Reg = (*AI).id();
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BBSize;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index d01de29826cad..3b7efe85fcff7 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -4192,9 +4192,8 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
EntryBB->end());
// Update the live-in information for the new entry block.
- for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
+ for (const MCRegister LiveIn : EntryBB->liveins())
NewEntryBB.addLiveIn(LiveIn);
- NewEntryBB.sortUniqueLiveIns();
// Get rid of the now empty basic block.
EntryBB->removeSuccessor(&NewEntryBB);
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 3485a27335f13..dca5aed81199a 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -370,7 +370,7 @@ void LiveIntervals::computeLiveInRegUnits() {
SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
for (const auto &LI : MBB.liveins()) {
- for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
+ for (MCRegUnit Unit : TRI->regunits(LI)) {
LiveRange *LR = RegUnitRanges[Unit];
if (!LR) {
// Use segment set to speed-up initial computation of the live range.
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
index f5677bcd6b5f9..2127c3fd5ccf8 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -153,21 +153,8 @@ bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
/// Add live-in registers of basic block \p MBB to \p LiveRegs.
void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
- for (const auto &LI : MBB.liveins()) {
- MCRegister Reg = LI.PhysReg;
- LaneBitmask Mask = LI.LaneMask;
- MCSubRegIndexIterator S(Reg, TRI);
- assert(Mask.any() && "Invalid livein mask");
- if (Mask.all() || !S.isValid()) {
- addReg(Reg);
- continue;
- }
- for (; S.isValid(); ++S) {
- unsigned SI = S.getSubRegIndex();
- if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
- addReg(S.getSubReg());
- }
- }
+ for (const MCRegister Reg : MBB.liveins())
+ addReg(Reg);
}
/// Adds all callee saved registers to \p LiveRegs.
diff --git a/llvm/lib/CodeGen/LiveRegUnits.cpp b/llvm/lib/CodeGen/LiveRegUnits.cpp
index 34de09dd2944b..f88aee1933882 100644
--- a/llvm/lib/CodeGen/LiveRegUnits.cpp
+++ b/llvm/lib/CodeGen/LiveRegUnits.cpp
@@ -88,7 +88,7 @@ void LiveRegUnits::accumulate(const MachineInstr &MI) {
static void addBlockLiveIns(LiveRegUnits &LiveUnits,
const MachineBasicBlock &MBB) {
for (const auto &LI : MBB.liveins())
- LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
+ LiveUnits.addRegMasked(LI, LaneBitmask::getAll());
}
/// Adds all callee saved registers to \p LiveUnits.
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index d50b7c0c24f86..20702eff4d910 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -576,9 +576,8 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
// Mark live-in registers as live-in.
SmallVector<Register, 4> Defs;
for (const auto &LI : MBB->liveins()) {
- assert(LI.PhysReg.isPhysical() &&
- "Cannot have a live-in virtual register!");
- HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
+ assert(LI.isPhysical() && "Cannot have a live-in virtual register!");
+ HandlePhysRegDef(LI, nullptr, Defs);
}
// Loop over all of the instructions, processing them.
@@ -612,9 +611,9 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
if (SuccMBB->isEHPad())
continue;
for (const auto &LI : SuccMBB->liveins()) {
- if (!TRI->isInAllocatableClass(LI.PhysReg))
+ if (!TRI->isInAllocatableClass(LI))
// Ignore other live-ins, e.g. those that are live into landing pads.
- LiveOuts.insert(LI.PhysReg);
+ LiveOuts.insert(LI);
}
}
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 96ba475f93844..019eae93edb4b 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -769,13 +769,11 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
OS.indent(2) << "liveins: ";
bool First = true;
- for (const auto &LI : MBB.liveins_dbg()) {
+ for (const Register Reg : MBB.liveins_dbg()) {
if (!First)
OS << ", ";
First = false;
- OS << printReg(LI.PhysReg, &TRI);
- if (!LI.LaneMask.all())
- OS << ":0x" << PrintLaneMask(LI.LaneMask);
+ OS << printReg(Reg, &TRI);
}
OS << "\n";
HasLineAttributes = true;
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 417ef3c028b25..f622d90d33920 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -56,7 +56,6 @@ MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
Insts.Parent = this;
if (B)
IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight();
- LiveInRegUnits.resize(MF.getSubtarget().getRegisterInfo()->getNumRegUnits());
}
MachineBasicBlock::~MachineBasicBlock() = default;
@@ -428,10 +427,8 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS.indent(2) << "liveins: ";
ListSeparator LS;
- for (const auto &LI : liveins()) {
- OS << LS << printReg(LI.PhysReg, TRI);
- if (!LI.LaneMask.all())
- OS << ":0x" << PrintLaneMask(LI.LaneMask);
+ for (const MCRegister Reg : liveins()) {
+ OS << LS << printReg(Reg, TRI);
}
HasLineAttributes = true;
}
@@ -599,76 +596,63 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
printName(OS, 0);
}
-void MachineBasicBlock::addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask) {
+void MachineBasicBlock::addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask) {
const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
- for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
- LaneBitmask UnitMask = (*Unit).second;
- if ((UnitMask & LaneMask).any())
- LiveInRegUnits.set((*Unit).first);
+ for (MCRegUnitMaskIterator U(PhysReg, TRI); U.isValid(); ++U) {
+ LaneBitmask Mask = (*U).second;
+ MCRegUnit Unit = (*U).first;
+ if ((Mask & LaneMask).any())
+ for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+ ++RootReg)
+ LiveIns.insert(*RootReg);
}
}
void MachineBasicBlock::removeLiveIn(MCRegister Reg, LaneBitmask LaneMask) {
- LiveInVector::iterator I = find_if(
- LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
- if (I == LiveIns.end())
- return;
-
- I->LaneMask &= ~LaneMask;
- if (I->LaneMask.none()) {
- LiveIns.erase(I);
- removeLiveInRegUnit(I->PhysReg);
+ // If LaneMask is all, add entire reg as itself, rather than its regUnits.
+ const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
+ for (MCRegUnitMaskIterator U(Reg, TRI); U.isValid(); ++U) {
+ LaneBitmask Mask = (*U).second;
+ MCRegUnit Unit = (*U).first;
+ if ((Mask & LaneMask).any())
+ for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+ ++RootReg)
+ LiveIns.erase(*RootReg);
}
}
MachineBasicBlock::livein_iterator
MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
- // Get non-const version of iterator.
- LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin());
- removeLiveInRegUnit(LI->PhysReg);
- return LiveIns.erase(LI);
-}
+ if (I == LiveIns.end())
+ return I;
-void MachineBasicBlock::removeLiveInRegUnit(MCRegister Reg) {
- const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
- for (MCRegUnit Unit : TRI->regunits(Reg))
- LiveInRegUnits.reset(Unit);
+ DenseSet<MCRegister>::iterator start = LiveIns.begin();
+ while (start != I)
+ start++;
+ MachineBasicBlock::livein_iterator next = start;
+ LiveIns.erase(start);
+ return next++;
}
bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
- for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
- LaneBitmask UnitMask = (*Unit).second;
- if ((UnitMask & LaneMask).any() && LiveInRegUnits.test((*Unit).first))
- return true;
+ for (MCRegUnitMaskIterator U(Reg, TRI); U.isValid(); ++U) {
+ LaneBitmask Mask = (*U).second;
+ MCRegUnit Unit = (*U).first;
+ if ((Mask & LaneMask).any()) {
+ for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+ ++RootReg)
+ if (LiveIns.count(*RootReg))
+ return true;
+ }
}
return false;
}
-void MachineBasicBlock::sortUniqueLiveIns() {
- llvm::sort(LiveIns,
- [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
- return LI0.PhysReg < LI1.PhysReg;
- });
- // Liveins are sorted by physreg now we can merge their lanemasks.
- LiveInVector::const_iterator I = LiveIns.begin();
- LiveInVector::const_iterator J;
- LiveInVector::iterator Out = LiveIns.begin();
- for (; I != LiveIns.end(); ++Out, I = J) {
- MCRegister PhysReg = I->PhysReg;
- LaneBitmask LaneMask = I->LaneMask;
- for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
- LaneMask |= J->LaneMask;
- Out->PhysReg = PhysReg;
- Out->LaneMask = LaneMask;
- }
- LiveIns.erase(Out, LiveIns.end());
-}
-
Register
MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
assert(getParent() && "MBB must be inserted in function");
- assert(PhysReg.isPhysical() && "Expected physreg");
+ assert(PhysReg && "Expected physreg");
assert(RC && "Register class is required");
assert((isEHPad() || this == &getParent()->front()) &&
"Only the entry block and landing pads can have physreg live ins");
@@ -1689,8 +1673,8 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
// no successor has it live in.
if (I == end()) {
for (MachineBasicBlock *S : successors()) {
- for (const MachineBasicBlock::RegisterMaskPair &LI : S->liveins()) {
- if (TRI->regsOverlap(LI.PhysReg, Reg))
+ for (const MCRegister LI : S->liveins()) {
+ if (TRI->regsOverlap(LI, Reg))
return LQR_Live;
}
}
@@ -1748,8 +1732,8 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
// Did we get to the start of the block?
if (I == begin()) {
// If so, the register's state is definitely defined by the live-in state.
- for (const MachineBasicBlock::RegisterMaskPair &LI : liveins())
- if (TRI->regsOverlap(LI.PhysReg, Reg))
+ for (const MCRegister LI : liveins())
+ if (TRI->regsOverlap(LI, Reg))
return LQR_Live;
return LQR_Dead;
@@ -1775,14 +1759,11 @@ MachineBasicBlock::getEndClobberMask(const TargetRegisterInfo *TRI) const {
void MachineBasicBlock::clearLiveIns() {
LiveIns.clear();
- LiveInRegUnits.reset();
}
-void MachineBasicBlock::clearLiveIns(
- std::vector<RegisterMaskPair> &OldLiveIns) {
+void MachineBasicBlock::clearLiveIns(DenseSet<MCRegister> &OldLiveIns) {
assert(OldLiveIns.empty() && "Vector must be empty");
- std::swap(LiveIns, OldLiveIns);
- LiveInRegUnits.reset();
+ LiveIns.swap(OldLiveIns);
}
MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const {
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 1105b8c15515f..66279fd109d71 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -553,7 +553,7 @@ void MachineCopyPropagation::readSuccessorLiveIns(
// If a copy result is livein to a successor, it is not dead.
for (const MachineBasicBlock *Succ : MBB.successors()) {
for (const auto &LI : Succ->liveins()) {
- for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
+ for (MCRegUnit Unit : TRI->regunits(LI)) {
if (MachineInstr *Copy = Tracker.findCopyForUnit(Unit, *TRI))
MaybeDeadCopies.remove(Copy);
}
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 1ac1a770ae72f..1c9575fa03aff 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -631,7 +631,7 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop,
// FIXME: That means a reload that're reused in successor block(s) will not
// be LICM'ed.
for (const auto &LI : BB->liveins()) {
- for (MCRegUnitIterator RUI(LI.PhysReg, TRI); RUI.isValid(); ++RUI)
+ for (MCRegUnitIterator RUI(LI, TRI); RUI.isValid(); ++RUI)
RUDefs.set(*RUI);
}
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 173193bb6266c..5b25b266d159b 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -2189,7 +2189,6 @@ static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
SuccBB->removeLiveIn(S);
for (auto U : UsedOpsInCopy)
SuccBB->addLiveIn(MI->getOperand(U).getReg());
- SuccBB->sortUniqueLiveIns();
}
static bool hasRegisterDependency(MachineInstr *MI,
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 87d3033038414..14a2c3d695402 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -155,10 +155,14 @@ struct MachineVerifier {
SlotIndex lastIndex;
// Add Reg and any sub-registers to RV
- void addRegWithSubRegs(RegVector &RV, Register Reg) {
+ void addRegUnitRoots(RegVector &RV, Register Reg) {
RV.push_back(Reg);
- if (Reg.isPhysical())
- append_range(RV, TRI->subregs(Reg.asMCReg()));
+ if (Reg.isPhysical()) {
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
+ for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+ ++RootReg)
+ RV.push_back(*RootReg);
+ }
}
struct BBInfo {
@@ -736,13 +740,13 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
// If this block has allocatable physical registers live-in, check that
// it is an entry block or landing pad.
for (const auto &LI : MBB->liveins()) {
- if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
+ if (isAllocatable(LI) && !MBB->isEHPad() &&
MBB->getIterator() != MBB->getParent()->begin() &&
!MBB->isInlineAsmBrIndirectTarget()) {
report("MBB has allocatable live-in, but isn't entry, landing-pad, or "
"inlineasm-br-indirect-target.",
MBB);
- report_context(LI.PhysReg);
+ report_context(LI);
}
}
}
@@ -903,20 +907,24 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
regsLive.clear();
if (MRI->tracksLiveness()) {
for (const auto &LI : MBB->liveins()) {
- if (!LI.PhysReg.isPhysical()) {
+ if (!LI.isPhysical()) {
report("MBB live-in list contains non-physical register", MBB);
continue;
}
- for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
- regsLive.insert(SubReg);
+ for (MCRegUnit Unit : TRI->regunits(LI))
+ for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+ ++RootReg)
+ regsLive.insert(*RootReg);
}
}
const MachineFrameInfo &MFI = MF->getFrameInfo();
BitVector PR = MFI.getPristineRegs(*MF);
for (unsigned I : PR.set_bits()) {
- for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
- regsLive.insert(SubReg);
+ for (MCRegUnit Unit : TRI->regunits(I))
+ for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+ ++RootReg)
+ regsLive.insert(*RootReg);
}
regsKilled.clear();
@@ -2969,7 +2977,7 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
// Both use and def operands can read a register.
if (MO->readsReg()) {
if (MO->isKill())
- addRegWithSubRegs(regsKilled, Reg);
+ addRegUnitRoots(regsKilled, Reg);
// Check that LiveVars knows this kill (unless we are inside a bundle, in
// which case we have already checked that LiveVars knows any kills on the
@@ -3042,13 +3050,13 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
bool Bad = !isReserved(Reg);
// We are fine if just any subregister has a defined value.
if (Bad) {
-
- for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
- if (regsLive.count(SubReg)) {
- Bad = false;
- break;
- }
- }
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
+ for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+ ++RootReg)
+ if (regsLive.count(*RootReg)) {
+ Bad = false;
+ break;
+ }
}
// If there is an additional implicit-use of a super register we stop
// here. By definition we are fine if the super register is not
@@ -3091,9 +3099,9 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
// Register defined.
// TODO: verify that earlyclobber ops are not used.
if (MO->isDead())
- addRegWithSubRegs(regsDead, Reg);
+ addRegUnitRoots(regsDead, Reg);
else
- addRegWithSubRegs(regsDefined, Reg);
+ addRegUnitRoots(regsDefined, Reg);
// Verify SSA form.
if (MRI->isSSA() && Reg.isVirtual() &&
@@ -3473,8 +3481,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
// reserved, which could mean a condition code register for instance.
if (MRI->tracksLiveness())
for (const auto &MBB : *MF)
- for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
- MCRegister LiveInReg = P.PhysReg;
+ for (MCRegister LiveInReg : MBB.liveins()) {
bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
continue;
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 9b852c0fd49cf..766b90f98eff6 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1248,8 +1248,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
// Get a list of registers that are used.
BitVector LiveIns(TRI.getNumRegs());
- for (const MachineBasicBlock::RegisterMaskPair &LI : MF.front().liveins())
- LiveIns.set(LI.PhysReg);
+ for (const MCRegister &LI : MF.front().liveins())
+ LiveIns.set(LI);
BitVector RegsToZero(TRI.getNumRegs());
for (MCRegister Reg : AllocatableSet.set_bits()) {
diff --git a/llvm/lib/CodeGen/RDFGraph.cpp b/llvm/lib/CodeGen/RDFGraph.cpp
index 805b0ee7be0bc..3c883b426e104 100644
--- a/llvm/lib/CodeGen/RDFGraph.cpp
+++ b/llvm/lib/CodeGen/RDFGraph.cpp
@@ -915,8 +915,8 @@ void DataFlowGraph::build(const Config &config) {
for (std::pair<MCRegister, Register> P : MRI.liveins())
LiveIns.insert(RegisterRef(P.first));
if (MRI.tracksLiveness()) {
- for (auto I : EntryB.liveins())
- LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask));
+ for (auto Reg : EntryB.liveins())
+ LiveIns.insert(RegisterRef(Reg));
}
// Add function-entry phi nodes for the live-in registers.
diff --git a/llvm/lib/CodeGen/RDFLiveness.cpp b/llvm/lib/CodeGen/RDFLiveness.cpp
index 682d316a5bfac..c66e19e619a02 100644
--- a/llvm/lib/CodeGen/RDFLiveness.cpp
+++ b/llvm/lib/CodeGen/RDFLiveness.cpp
@@ -871,8 +871,8 @@ void Liveness::computeLiveIns() {
// Dump the liveness map
for (MachineBasicBlock &B : MF) {
std::vector<RegisterRef> LV;
- for (const MachineBasicBlock::RegisterMaskPair &LI : B.liveins())
- LV.push_back(RegisterRef(LI.PhysReg, LI.LaneMask));
+ for (const MCRegister LI : B.liveins())
+ LV.push_back(RegisterRef(LI));
llvm::sort(LV, std::less<RegisterRef>(PRI));
dbgs() << printMBBReference(B) << "\t rec = {";
for (auto I : LV)
@@ -896,14 +896,14 @@ void Liveness::resetLiveIns() {
for (auto &B : DFG.getMF()) {
// Remove all live-ins.
std::vector<MCRegister> T;
- for (const MachineBasicBlock::RegisterMaskPair &LI : B.liveins())
- T.push_back(LI.PhysReg);
+ for (const MCRegister LI : B.liveins())
+ T.push_back(LI);
for (auto I : T)
B.removeLiveIn(I);
// Add the newly computed live-ins.
const RegisterAggr &LiveIns = LiveMap[&B];
for (RegisterRef R : LiveIns.refs())
- B.addLiveIn({MCPhysReg(R.Reg), R.Mask});
+ B.addLiveIn({MCPhysReg(R.Reg)});
}
}
@@ -914,18 +914,8 @@ void Liveness::resetKills() {
void Liveness::resetKills(MachineBasicBlock *B) {
auto CopyLiveIns = [this](MachineBasicBlock *B, BitVector &LV) -> void {
- for (auto I : B->liveins()) {
- MCSubRegIndexIterator S(I.PhysReg, &TRI);
- if (!S.isValid()) {
- LV.set(I.PhysReg.id());
- continue;
- }
- do {
- LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
- if ((M & I.LaneMask).any())
- LV.set(S.getSubReg());
- ++S;
- } while (S.isValid());
+ for (auto Reg : B->liveins()) {
+ LV.set(Reg);
}
};
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index 415674231b5cb..da4f3bf7fb922 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -81,7 +81,7 @@ void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
// This is the entry block.
if (MBB->pred_empty()) {
for (const auto &LI : MBB->liveins()) {
- for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
+ for (MCRegUnit Unit : TRI->regunits(LI)) {
// Treat function live-ins as if they were defined just before the first
// instruction. Usually, function arguments are set up immediately
// before the call.
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index fb960711d4ae0..dc6306ef2fdd4 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -670,8 +670,7 @@ void RegAllocFastImpl::reloadAtBegin(MachineBasicBlock &MBB) {
if (LiveVirtRegs.empty())
return;
- for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
- MCRegister Reg = P.PhysReg;
+ for (MCRegister Reg : MBB.liveins()) {
// Set state to live-in. This possibly overrides mappings to virtual
// registers but we don't care anymore at this point.
setPhysRegState(Reg, regLiveIn);
@@ -1763,7 +1762,7 @@ void RegAllocFastImpl::allocateBasicBlock(MachineBasicBlock &MBB) {
assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?");
for (const auto &LiveReg : MBB.liveouts())
- setPhysRegState(LiveReg.PhysReg, regPreAssigned);
+ setPhysRegState(LiveReg, regPreAssigned);
Coalesced.clear();
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index a26804707dd1f..15c2ead9e5655 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -236,10 +236,9 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
// uses all the registers that are livein to the successor blocks.
for (const MachineBasicBlock *Succ : BB->successors()) {
for (const auto &LI : Succ->liveins()) {
- for (MCRegUnitMaskIterator U(LI.PhysReg, TRI); U.isValid(); ++U) {
- auto [Unit, Mask] = *U;
- if ((Mask & LI.LaneMask).any() && !Uses.contains(Unit))
- Uses.insert(PhysRegSUOper(&ExitSU, -1, Unit));
+ for (MCRegUnitIterator Unit(LI, TRI); Unit.isValid(); ++Unit) {
+ if (!Uses.contains(*Unit))
+ Uses.insert(PhysRegSUOper(&ExitSU, -1, *Unit));
}
}
}
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index fa57eb30fac43..6ac6bdedff232 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -495,8 +495,8 @@ tryToSplitRestore(MachineBasicBlock *MBB,
// interfere with control flow optimizer decisions.
MF->insert(MF->end(), NMBB);
- for (const MachineBasicBlock::RegisterMaskPair &LI : MBB->liveins())
- NMBB->addLiveIn(LI.PhysReg);
+ for (const MCRegister LI : MBB->liveins())
+ NMBB->addLiveIn(LI);
TII->insertUnconditionalBranch(*NMBB, MBB, DebugLoc());
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 0fc3e5d9a3052..01457ac9f28ee 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -395,11 +395,6 @@ void VirtRegRewriter::addMBBLiveIns() {
}
}
}
-
- // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
- // each MBB's LiveIns set before calling addLiveIn on them.
- for (MachineBasicBlock &MBB : *MF)
- MBB.sortUniqueLiveIns();
}
/// Returns true if the given machine operand \p MO only reads undefined lanes.
diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
index 4d0d99bce258a..2c68a42663f96 100644
--- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
@@ -542,7 +542,7 @@ bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
// Live-out registers are used.
for (const MachineBasicBlock *Succ : MBB.successors()) {
for (const auto &LI : Succ->liveins()) {
- int RegIdx = mapRegToGPRIndex(LI.PhysReg);
+ int RegIdx = mapRegToGPRIndex(LI);
if (RegIdx >= 0)
LOHInfos[RegIdx].OneUser = true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 1761f58faf0fe..10a34e9b4b224 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3310,12 +3310,10 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
AFI->setVGIdx(RPI.FrameIdx);
} else {
const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
- if (llvm::any_of(
- MBB.liveins(),
- [&STI](const MachineBasicBlock::RegisterMaskPair &LiveIn) {
- return STI.getRegisterInfo()->isSuperOrSubRegisterEq(
- AArch64::X0, LiveIn.PhysReg);
- }))
+ if (llvm::any_of(MBB.liveins(), [&STI](const MCRegister &LiveIn) {
+ return STI.getRegisterInfo()->isSuperOrSubRegisterEq(AArch64::X0,
+ LiveIn);
+ }))
X0Scratch = Reg1;
if (X0Scratch != AArch64::NoRegister)
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 97736e2410c18..d4617f77f47ce 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -995,8 +995,6 @@ void SIFrameLowering::emitCSRSpillStores(
for (MachineBasicBlock &MBB : MF) {
for (MCPhysReg Reg : ScratchSGPRs)
MBB.addLiveIn(Reg);
-
- MBB.sortUniqueLiveIns();
}
if (!LiveUnits.empty()) {
for (MCPhysReg Reg : ScratchSGPRs)
@@ -1400,8 +1398,6 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
for (MCPhysReg Reg : FuncInfo->getAGPRSpillVGPRs())
MBB.addLiveIn(Reg);
- MBB.sortUniqueLiveIns();
-
if (!SpillFIs.empty() && SeenDbgInstr) {
// FIXME: The dead frame indices are replaced with a null register from
// the debug value instructions. We should instead, update it with the
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index d27c523425feb..ee4f6e2e7f475 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -222,7 +222,6 @@ static void updateLiveness(MachineFunction &MF, ArrayRef<CalleeSavedInfo> CSI) {
for (const CalleeSavedInfo &CSIReg : CSI)
EntryBB.addLiveIn(CSIReg.getReg());
- EntryBB.sortUniqueLiveIns();
}
bool SILowerSGPRSpills::spillCalleeSavedRegs(
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index a83fc2d188de2..958db3a139f74 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -362,7 +362,6 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(
for (MachineBasicBlock &MBB : MF) {
MBB.removeLiveIn(Reg);
- MBB.sortUniqueLiveIns();
}
Reg = NewReg;
@@ -409,7 +408,6 @@ bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
reserveWWMRegister(LaneVGPR);
for (MachineBasicBlock &MBB : MF) {
MBB.addLiveIn(LaneVGPR);
- MBB.sortUniqueLiveIns();
}
SpillPhysVGPRs.push_back(LaneVGPR);
} else {
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index e41e02a560db0..6cbefd0f16a7b 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -2503,8 +2503,8 @@ MachineBasicBlock *ARMConstantIslands::adjustJTTargetBlockForward(
MF->insert(MBBI, NewBB);
// Copy live-in information to new block.
- for (const MachineBasicBlock::RegisterMaskPair &RegMaskPair : BB->liveins())
- NewBB->addLiveIn(RegMaskPair);
+ for (const MCRegister Reg : BB->liveins())
+ NewBB->addLiveIn(Reg);
// Add an unconditional branch from NewBB to BB.
// There doesn't seem to be meaningful DebugInfo available; this doesn't
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 6e885ab574cea..5791f29f02b36 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -3229,8 +3229,6 @@ void ARMFrameLowering::adjustForSegmentedStacks(
}
for (MachineBasicBlock *MBB : BeforePrologueRegion) {
- // Make sure the LiveIns are still sorted and unique.
- MBB->sortUniqueLiveIns();
// Replace the edges to PrologueMBB by edges to the sequences
// we are about to add, but only update for immediate predecessors.
if (MBB->isSuccessor(&PrologueMBB))
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 79cfac31e2d0e..ab8c4e738b760 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -1015,17 +1015,17 @@ bool LowOverheadLoop::ValidateLiveOuts() {
assert(ML.getNumBlocks() == 1 && "Expected single block loop!");
assert(ExitBlocks.size() == 1 && "Expected a single exit block");
MachineBasicBlock *ExitBB = ExitBlocks.front();
- for (const MachineBasicBlock::RegisterMaskPair &RegMask : ExitBB->liveins()) {
+ for (const MCRegister Reg : ExitBB->liveins()) {
// TODO: Instead of blocking predication, we could move the vctp to the exit
// block and calculate it's operand there in or the preheader.
- if (RegMask.PhysReg == ARM::VPR) {
+ if (Reg == ARM::VPR) {
LLVM_DEBUG(dbgs() << " VPR is live in to the exit block.");
return false;
}
// Check Q-regs that are live in the exit blocks. We don't collect scalars
// because they won't be affected by lane predication.
- if (QPRs->contains(RegMask.PhysReg))
- if (auto *MI = RDA.getLocalLiveOutMIDef(Header, RegMask.PhysReg))
+ if (QPRs->contains(Reg))
+ if (auto *MI = RDA.getLocalLiveOutMIDef(Header, Reg))
LiveOutMIs.insert(MI);
}
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
index 911502605c227..57fe8a6058dcd 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
@@ -196,7 +196,7 @@ static void emitThumbRegPlusImmInReg(
}
// If there's no use or def of CPSR then it may be live if it's a
// live-out value.
- auto liveOutIsCpsr = [](auto &Out) { return Out.PhysReg == ARM::CPSR; };
+ auto liveOutIsCpsr = [](auto &Out) { return Out == ARM::CPSR; };
if (!LiveCpsr && !CpsrWrite)
LiveCpsr = any_of(MBB.liveouts(), liveOutIsCpsr);
diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
index b919be3d4466d..4784379b84c65 100644
--- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
@@ -261,7 +261,7 @@ bool AVRFrameLowering::spillCalleeSavedRegisters(
// add it to the livein list.
if (IsNotLiveIn)
for (const auto &LiveIn : MBB.liveins())
- if (STI.getRegisterInfo()->isSubRegister(LiveIn.PhysReg, Reg)) {
+ if (STI.getRegisterInfo()->isSubRegister(LiveIn, Reg)) {
IsNotLiveIn = false;
MBB.addLiveIn(Reg);
break;
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index eca5ac140f3c3..cfde51eadcb71 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -234,17 +234,8 @@ HexagonBlockRanges::RegisterSet HexagonBlockRanges::getLiveIns(
RegisterSet LiveIns;
RegisterSet Tmp;
- for (auto I : B.liveins()) {
- MCSubRegIndexIterator S(I.PhysReg, &TRI);
- if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) {
- Tmp.insert({I.PhysReg, 0});
- continue;
- }
- for (; S.isValid(); ++S) {
- unsigned SI = S.getSubRegIndex();
- if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())
- Tmp.insert({S.getSubReg(), 0});
- }
+ for (auto Reg : B.liveins()) {
+ Tmp.insert({Reg, 0});
}
for (auto R : Tmp) {
diff --git a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
index 7ec1b6a66d74a..e386a5c46cfeb 100644
--- a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
@@ -216,13 +216,12 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
// Correct live-in information. Is used by post-RA scheduler
// The live-in to LayoutSucc is now all values live-in to
// JumpAroundTarget.
- std::vector<MachineBasicBlock::RegisterMaskPair> OrigLiveIn(
- LayoutSucc->livein_begin(), LayoutSucc->livein_end());
- std::vector<MachineBasicBlock::RegisterMaskPair> NewLiveIn(
- JumpAroundTarget->livein_begin(),
- JumpAroundTarget->livein_end());
+ DenseSet<MCRegister> OrigLiveIn(LayoutSucc->livein_begin(),
+ LayoutSucc->livein_end());
+ DenseSet<MCRegister> NewLiveIn(JumpAroundTarget->livein_begin(),
+ JumpAroundTarget->livein_end());
for (const auto &OrigLI : OrigLiveIn)
- LayoutSucc->removeLiveIn(OrigLI.PhysReg);
+ LayoutSucc->removeLiveIn(OrigLI);
for (const auto &NewLI : NewLiveIn)
LayoutSucc->addLiveIn(NewLI);
}
diff --git a/llvm/lib/Target/M68k/M68kFrameLowering.cpp b/llvm/lib/Target/M68k/M68kFrameLowering.cpp
index ae2bb975bc9d6..afbeb05158760 100644
--- a/llvm/lib/Target/M68k/M68kFrameLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kFrameLowering.cpp
@@ -177,9 +177,7 @@ static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
static bool isRegLiveIn(MachineBasicBlock &MBB, unsigned Reg) {
return llvm::any_of(MBB.liveins(),
- [Reg](MachineBasicBlock::RegisterMaskPair RegMask) {
- return RegMask.PhysReg == Reg;
- });
+ [Reg](MCRegister RegVal) { return RegVal == Reg; });
}
uint64_t
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 258010d331181..baf3296aab12f 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -401,8 +401,8 @@ void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
const MachineBasicBlock &SuccBB) {
for (const MachineBasicBlock *S : MBB.successors())
if (S != &SuccBB)
- for (const auto &LI : S->liveins())
- Uses.set(LI.PhysReg.id());
+ for (const MCRegister LI : S->liveins())
+ Uses.set(LI.id());
}
bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 24129de9b7171..73e1a2f016f07 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -126,7 +126,7 @@ namespace {
unsigned Mask = 0;
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin();
I != MBB->livein_end(); ) {
- MCPhysReg Reg = I->PhysReg;
+ MCPhysReg Reg = *I;
static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
Mask |= 1 << (Reg - X86::FP0);
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index 68bf1d09d1093..07bab5d22f0d5 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -173,8 +173,7 @@ static unsigned getPOP2Opcode(const X86Subtarget &ST) {
}
static bool isEAXLiveIn(MachineBasicBlock &MBB) {
- for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
- MCRegister Reg = RegMask.PhysReg;
+ for (MCRegister Reg : MBB.liveins()) {
if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
Reg == X86::AH || Reg == X86::AL)
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
index e4fe27f010c2f..df486a801a8b1 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
@@ -104,7 +104,7 @@ class LoopSnippetRepetitor : public SnippetRepetitor {
Loop.MBB->addLiveIn(LoopCounter);
for (MCRegister Reg : Filler.getRegistersSetUp())
Loop.MBB->addLiveIn(Reg);
- for (const auto &LiveIn : Entry.MBB->liveins())
+ for (const MCRegister LiveIn : Entry.MBB->liveins())
Loop.MBB->addLiveIn(LiveIn);
}
for (auto _ : seq(LoopUnrollFactor)) {
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp
index 41ee4028051bb..d4ebbfd6b4d01 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp
@@ -66,10 +66,6 @@ static auto HasOpcode = [](unsigned Opcode) {
return Property(&MachineInstr::getOpcode, Eq(Opcode));
};
-static auto LiveReg = [](unsigned Reg) {
- return Field(&MachineBasicBlock::RegisterMaskPair::PhysReg, Eq(Reg));
-};
-
TEST_F(X86SnippetRepetitorTest, Duplicate) {
TestCommon(Benchmark::Duplicate);
// Duplicating creates a single basic block that repeats the instructions.
@@ -101,12 +97,11 @@ TEST_F(X86SnippetRepetitorTest, Loop) {
HasOpcode(X86::NOOP), HasOpcode(X86::NOOP),
HasOpcode(X86::NOOP), HasOpcode(X86::ADD64ri8),
HasOpcode(X86::JCC_1)));
- EXPECT_THAT(
- LoopBlock.liveins(),
- UnorderedElementsAre(
- LiveReg(X86::EAX),
- LiveReg(State.getExegesisTarget().getDefaultLoopCounterRegister(
- State.getTargetMachine().getTargetTriple()))));
+ EXPECT_THAT(LoopBlock.liveins(),
+ UnorderedElementsAre(
+ MCRegister(X86::EAX),
+ State.getExegesisTarget().getDefaultLoopCounterRegister(
+ State.getTargetMachine().getTargetTriple())));
EXPECT_THAT(MF->getBlockNumbered(2)->instrs(),
ElementsAre(HasOpcode(X86::RET64)));
}
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