[llvm] f46ff4c - [NFC][regalloc] Fix typo in llvm/lib/CodeGen/AllocationOrder.h.

Jim Lin via llvm-commits llvm-commits at lists.llvm.org
Thu May 1 19:23:48 PDT 2025


Author: Jim Lin
Date: 2025-05-02T10:11:34+08:00
New Revision: f46ff4c204b622029b02d0c7d4ed47ad162521e8

URL: https://github.com/llvm/llvm-project/commit/f46ff4c204b622029b02d0c7d4ed47ad162521e8
DIFF: https://github.com/llvm/llvm-project/commit/f46ff4c204b622029b02d0c7d4ed47ad162521e8.diff

LOG: [NFC][regalloc] Fix typo in llvm/lib/CodeGen/AllocationOrder.h.

Added: 
    

Modified: 
    llvm/lib/CodeGen/AllocationOrder.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/AllocationOrder.h b/llvm/lib/CodeGen/AllocationOrder.h
index e0ea6a806a4b7..3dd02c3b14d3a 100644
--- a/llvm/lib/CodeGen/AllocationOrder.h
+++ b/llvm/lib/CodeGen/AllocationOrder.h
@@ -48,7 +48,7 @@ class LLVM_LIBRARY_VISIBILITY AllocationOrder {
   public:
     Iterator(const AllocationOrder &AO, int Pos) : AO(AO), Pos(Pos) {}
 
-    /// Return true if the curent position is that of a preferred register.
+    /// Return true if the current position is that of a preferred register.
     bool isHint() const { return Pos < 0; }
 
     /// Return the next physical register in the allocation order.
@@ -85,7 +85,7 @@ class LLVM_LIBRARY_VISIBILITY AllocationOrder {
                                 const RegisterClassInfo &RegClassInfo,
                                 const LiveRegMatrix *Matrix);
 
-  /// Create an AllocationOrder given the Hits, Order, and HardHits values.
+  /// Create an AllocationOrder given the Hints, Order, and HardHints values.
   /// Use the create method above - the ctor is for unittests.
   AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order,
                   bool HardHints)


        


More information about the llvm-commits mailing list