[llvm] [TableGen][MacroFusion] Predicate if the first inst has the same register (PR #137778)

[Matt Arsenault via llvm-commits]

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@@ -55,11 +55,20 @@ class TieReg<int firstOpIdx, int secondOpIdx> : BothFusionPredicate {
   int SecondOpIdx = secondOpIdx;
 }
 
+// The operand of `FirstMI` at position `firstOpIdx` should be the same as the
+// operand at position `secondOpIdx`.
+// If the fusion has `IsCommutable` being true and the operand at `secondOpIdx`
+// has commutable operand, then the commutable operand will be checked too.
+class FirstSameReg<int firstOpIdx, int secondOpIdx> : FirstFusionPredicate {
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arsenm wrote:

It's doubly confusing because this is referring to first and second meaning the instructions and first and second as in the operands. What about

FirstInstOperandsAreSameReg, etc. 

https://github.com/llvm/llvm-project/pull/137778