[llvm] Address Codegen bug related to marking subregister MachineOperand defines as undef (PR #134929)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Thu May 1 01:21:15 PDT 2025


================
@@ -3979,6 +3979,32 @@ void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
       continue;
     LLVM_DEBUG(dbgs() << "  Rescheduling physreg copy ";
                DAG->dumpNode(*Dep.getSUnit()));
+
+    // Check to make sure that there are no subreg defintions of the given
+    // register between it's new and old location that are marked as undef. If
+    // so, mark the current instruction as undef instead.
+    SmallVector<MachineOperand *, 1> SubregDefs;
+    for (MachineOperand &MO : Copy->operands()) {
+      if (MO.isReg() && MO.isDef() && MO.getSubReg() != 0) {
+        SubregDefs.push_back(&MO);
+      }
+    }
+    if (SubregDefs.size()) {
+      for (auto CurrInst = InsertPos; CurrInst != Copy; ++CurrInst) {
----------------
arsenm wrote:

The starting MIR is correct, the new output with 2 undefs is wrong. When the first undef subregister def moves past the second, the undef flag needs to move to the first subregister def. They both should not end up with the undef flag 

https://github.com/llvm/llvm-project/pull/134929


More information about the llvm-commits mailing list